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[209.132.180.67]) by mx.google.com with ESMTP id u6-v6si5688145pld.628.2018.03.16.01.37.11; Fri, 16 Mar 2018 01:37:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@ffwll.ch header.s=google header.b=Ywizqnyv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753120AbeCPIgN (ORCPT + 99 others); Fri, 16 Mar 2018 04:36:13 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:55679 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751448AbeCPIgJ (ORCPT ); Fri, 16 Mar 2018 04:36:09 -0400 Received: by mail-wm0-f67.google.com with SMTP id q83so1482402wme.5 for ; Fri, 16 Mar 2018 01:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=sender:date:from:to:cc:subject:message-id:mail-followup-to :references:mime-version:content-disposition:in-reply-to:user-agent; bh=8SWcxwhPgXHCk5RZlM27Xtu08YGo3a+xQzEyjQz77V4=; b=Ywizqnyv8yqF2l1gtejsO5AuUmlMAFmsomMk+dBnOhgFQPVq7ZK7lTJpVFQdQjpdft BQnK+aOolzSgRapjVSneJi9kT9UGfFXZqLOEsKqVNsi0t3cgcb2YhJVKEIlV1l8jPqpe lZ/Auxp+OzODsc3TlJGBmpdNFQYy6/H8d8KOQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to:user-agent; bh=8SWcxwhPgXHCk5RZlM27Xtu08YGo3a+xQzEyjQz77V4=; b=UMARGyQ5WBDGH6wiEI+YagXoGQ5g2VwDKsTv1KQLy5CH07mcnqsVHrQ5tSs4K3iMEe W0XFdHphWWsRmxpx8zK5fXC+9cWasbsGKbhB11/ZuWXItlUQNFfY2Hi1GITyjFt8+leG S4wF4uW2tQ/M4CRsOX2ntdnsihKEKV3D5tU8Vq5Ig+dKYECv8h1DV8cSO9EXUDSaIXyG Cuz++OKz9bPlVvaKqaqxo+HTuQ+ylrjRDxLXYphKwtpRd1g687MLPbBJZ+sWQu/6okvW apSCLFrFIeJ7sBgyohZDnoy1bwoPJlTRHRixGz59ELFy8qWmH5KEkFc5MDvafkQrF8D/ NDpQ== X-Gm-Message-State: AElRT7GFN8LXESxoq7xFeubuq9EA5uVyCrt0YdGACCPX2PXwGnRm/9YJ BeM04IY9EkJuhfYlOO6DpM+JpQ== X-Received: by 10.80.135.11 with SMTP id i11mr1577496edb.233.1521189368148; Fri, 16 Mar 2018 01:36:08 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:56e6:0:e4bc:76a0:8042:669e]) by smtp.gmail.com with ESMTPSA id p91sm3578726edp.65.2018.03.16.01.36.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Mar 2018 01:36:07 -0700 (PDT) Date: Fri, 16 Mar 2018 09:36:04 +0100 From: Daniel Vetter To: Alexandru M Stan Cc: David Airlie , Rob Herring , Mark Rutland , Archit Taneja , Andrzej Hajda , Laurent Pinchart , Sean Paul , devicetree@vger.kernel.org, Enric Balletbo i Serra , Heiko Stuebner , briannorris@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, marcheu@chromium.org, hoegsberg@chromium.org, Thierry Escande , Jeffy Chen , Yakir Yang , Daniel Vetter , Marek Szyprowski , zain wang , Sylwester Nawrocki Subject: Re: [PATCH 2/2] drm/bridge: analogix: Enable EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU Message-ID: <20180316083604.GG25297@phenom.ffwll.local> Mail-Followup-To: Alexandru M Stan , David Airlie , Rob Herring , Mark Rutland , Archit Taneja , Andrzej Hajda , Laurent Pinchart , Sean Paul , devicetree@vger.kernel.org, Enric Balletbo i Serra , Heiko Stuebner , briannorris@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, marcheu@chromium.org, hoegsberg@chromium.org, Thierry Escande , Jeffy Chen , Yakir Yang , Marek Szyprowski , zain wang , Sylwester Nawrocki References: <20180316025659.217423-1-amstan@chromium.org> <20180316025659.217423-3-amstan@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180316025659.217423-3-amstan@chromium.org> X-Operating-System: Linux phenom 4.15.0-1-amd64 User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 15, 2018 at 07:56:59PM -0700, Alexandru M Stan wrote: > Configure the DPCD registers for the backlight to respect the pwm frequency > of the input. We sometimes don't want it to generate its own. > > Signed-off-by: Alexandru M Stan I wonder a bit whether we should have some generic infrastructure in the dp helpers itself to apply quirks like this. It's more-or-less what we have for EDID quirking. But then I guess for panels a lot of it is specific to the bridge/encoder/panel combo and given platform, so probably not much use for reuse across boards/platforms. External displays would be a different story. I guess you can count that as an Acked-by: Daniel Vetter on the overall thing, but pls get bridge folks to review this too. -Daniel > --- > > drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 48 ++++++++++++++++++++++ > drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 1 + > 2 files changed, 49 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 5c52307146c7..b830403be8eb 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -916,6 +916,46 @@ static irqreturn_t analogix_dp_irq_thread(int irq, void *arg) > return IRQ_HANDLED; > } > > +static int analogix_dp_backlight_pwm_passthru(struct analogix_dp_device *dp) > +{ > + u8 value; > + const u8 expected_cap = DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP | > + DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP; > + int ret = 0; > + > + ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP, > + &value); > + if (ret != 1) { > + DRM_DEV_ERROR(dp->dev, > + "backlight PWM passthru: Can't read BACKLIGHT_ADJUSTMENT_CAP\n"); > + return ret; > + } > + > + if ((value & expected_cap) != expected_cap) { > + DRM_DEV_ERROR(dp->dev, > + "panel doesn't support backlight PWM passthru, BACKLIGHT_ADJUSTMENT_CAP=0x%02x\n", > + value); > + return -1; > + } > + > + ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, > + &value); > + if (ret != 1) { > + DRM_DEV_ERROR(dp->dev, > + "backlight PWM passthru: Can't read BACKLIGHT_MODE_SET_REGISTER\n"); > + return ret; > + } > + > + value |= DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE; > + ret = drm_dp_dpcd_writeb(&dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, > + value); > + if (ret != 1) { > + DRM_DEV_ERROR(dp->dev, > + "backlight PWM passthru: Can't write BACKLIGHT_MODE_SET_REGISTER\n"); > + } > + return ret; > +} > + > static void analogix_dp_commit(struct analogix_dp_device *dp) > { > int ret; > @@ -954,6 +994,12 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) > dp->psr_enable = analogix_dp_detect_sink_psr(dp); > if (dp->psr_enable) > analogix_dp_enable_sink_psr(dp); > + > + if (dp->backlight_pwm_passthru) { > + if (analogix_dp_backlight_pwm_passthru(dp) != 1) > + DRM_DEV_ERROR(dp->dev, > + "Could not enable backlight pwm pin passthru.\n"); > + } > } > > /* > @@ -1424,6 +1470,8 @@ analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, > if (IS_ERR(dp->reg_base)) > return ERR_CAST(dp->reg_base); > > + dp->backlight_pwm_passthru = > + of_property_read_bool(dev->of_node, "backlight-pwm-passthru"); > dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd"); > > dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > index 6a96ef7e6934..aea51413e78e 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > @@ -171,6 +171,7 @@ struct analogix_dp_device { > struct phy *phy; > int dpms_mode; > int hpd_gpio; > + bool backlight_pwm_passthru; > bool force_hpd; > bool psr_enable; > bool fast_train_support; > -- > 2.13.5 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch