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[209.85.128.180]) by smtp.gmail.com with ESMTPSA id s8sm7927319edk.28.2018.03.18.19.14.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 18 Mar 2018 19:14:41 -0700 (PDT) Received: by mail-wr0-f180.google.com with SMTP id z8so7284062wrh.7; Sun, 18 Mar 2018 19:14:40 -0700 (PDT) X-Received: by 10.223.186.66 with SMTP id t2mr8549944wrg.155.1521425680472; Sun, 18 Mar 2018 19:14:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.164.129 with HTTP; Sun, 18 Mar 2018 19:14:19 -0700 (PDT) In-Reply-To: <20180318200715.363f3135@dell-desktop.home> References: <20180223133742.26044-1-mylene.josserand@bootlin.com> <20180223133742.26044-11-mylene.josserand@bootlin.com> <6329fbb6-13a1-41fe-f6cf-f2f0d4b2e5f9@arm.com> <20180318200715.363f3135@dell-desktop.home> From: Chen-Yu Tsai Date: Mon, 19 Mar 2018 10:14:19 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 10/10] ARM: sunxi: smp: Add initialization of CNTVOFF To: =?UTF-8?Q?Myl=C3=A8ne_Josserand?= Cc: Marc Zyngier , Maxime Ripard , Russell King , Rob Herring , Mark Rutland , devicetree , quentin.schulz@bootlin.com, linux-kernel , LABBE Corentin , Thomas Petazzoni , linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand wrote: > Hello Mark, > > Please, excuse me for this late answer and thank you for the review! > > On Wed, 7 Mar 2018 12:18:33 +0000 > Marc Zyngier wrote: > >> On 23/02/18 13:37, Mylène Josserand wrote: >> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized. >> >> Only on A7? Is that specific to your platform? > > I do not really know other Allwinner's platforms about this subject. At > least, the sun9i-a80 which is a Cortex-a15/a7 does not need that but it > is necessary for sun8i-a83t which is a cortex-a7. Maybe, Chen-Yu or > Maxime could help us on it. AFAIK all Allwinner CPUs need it if there isn't a firmware (PSCI) layer beneath the kernel that will do the setup. We just have "arm,cpu-registers-not-fw-configured" set for all the other SoCs that have in-kernel SMP support, which includes the A31, A23, A33 and A80. ChenYu