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[209.132.180.67]) by mx.google.com with ESMTP id y20-v6si1899167pll.287.2018.03.19.02.07.04; Mon, 19 Mar 2018 02:07:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BC5x3q7/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755423AbeCSJF7 (ORCPT + 99 others); Mon, 19 Mar 2018 05:05:59 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:28659 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751747AbeCSJF4 (ORCPT ); Mon, 19 Mar 2018 05:05:56 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w2J959JJ003100; Mon, 19 Mar 2018 04:05:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1521450309; bh=PSe2MXAHDSYURgXHcemFxeB9hC3uUO/VNRU5TmD7XTo=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=BC5x3q7/gTyhRSXPUT7WsasqIEVk25vtju3XwP29wSSzUPWFHg2dhYg119rL01MeD pTJv6ibBz94As+Mbkusli2Rpr3vtArZj29uJdiNzoZnKDCPjv7f1FwErRJWdiERQBJ gfaf09LQDJR+3lSRicKPx72T8kEcvwBTFibdVb28= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2J9593C026996; Mon, 19 Mar 2018 04:05:09 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 19 Mar 2018 04:05:08 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 19 Mar 2018 04:05:08 -0500 Received: from [10.1.3.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2J956kH029124; Mon, 19 Mar 2018 04:05:07 -0500 Subject: Re: [PATCH] drm/tilcdc: Fix setting clock divider for omap-l138 To: David Lechner , CC: Tomi Valkeinen , Bartosz Golaszewski , Sekhar Nori , References: <1521068325-15077-1-git-send-email-david@lechnology.com> From: Jyri Sarha Message-ID: Date: Mon, 19 Mar 2018 11:05:06 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1521068325-15077-1-git-send-email-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-GB Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks, I'll pick this for v4.18. Best regards, Jyri On 15/03/18 00:58, David Lechner wrote: > This fixes setting the clock divider on the TI OMAP-L138 LCDK board. > > The clock drivers for OMAP-L138 are being covernted to the common clock > framework. When this happens, clk_set_rate() will no longer return an > error. However, on this SoC, the clock rate cannot actually be changed > because the clock has to maintain a fixed ratio to the ARM clock. So > after attempting to set the clock rate, we need to check to see if the > new rate is actually close enough. If not, then follow the previous > error path to adjust the divider in LCDC IP block to compensate for not > being able to change the parent clock rate. > > Tested working on a TI OMAP-L138 LCDK board. > > Signed-off-by: David Lechner > --- > drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > index 8bf6bb9..6931777 100644 > --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c > @@ -224,7 +224,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) > > ret = clk_set_rate(priv->clk, req_rate * clkdiv); > clk_rate = clk_get_rate(priv->clk); > - if (ret < 0) { > + if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { > /* > * If we fail to set the clock rate (some architectures don't > * use the common clock framework yet and may not implement > -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. 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