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[209.132.180.67]) by mx.google.com with ESMTP id y1si5836477pgq.423.2018.03.19.02.51.51; Mon, 19 Mar 2018 02:52:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932737AbeCSJu0 (ORCPT + 99 others); Mon, 19 Mar 2018 05:50:26 -0400 Received: from foss.arm.com ([217.140.101.70]:50694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932682AbeCSJuW (ORCPT ); Mon, 19 Mar 2018 05:50:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC76880D; Mon, 19 Mar 2018 02:50:21 -0700 (PDT) Received: from [10.1.206.73] (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9EFDF3F592; Mon, 19 Mar 2018 02:50:19 -0700 (PDT) Subject: Re: [PATCH v11 8/8] perf: ARM DynamIQ Shared Unit PMU support To: Saravana Kannan Cc: Mark Rutland , robh@kernel.org, mathieu.poirier@linaro.org, peterz@infradead.org, sudeep.holla@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, marc.zyngier@arm.com, jonathan.cameron@huawei.com, frowand.list@gmail.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org References: <20180102112533.13640-1-suzuki.poulose@arm.com> <20180102112533.13640-9-suzuki.poulose@arm.com> <5A90B77E.8040105@codeaurora.org> <20180225143653.peb4quk3ha5h3t5x@salmiak> <5A972A7D.9020301@codeaurora.org> <20180301114911.fundyuqxtj5klk4e@lakrids.cambridge.arm.com> <5A986425.9080007@codeaurora.org> <20180302104223.7tpsyhsum7nej237@lakrids.cambridge.arm.com> <5A99A3DC.9020400@codeaurora.org> <20180305105925.4cjiqejfid7rswe6@lakrids.cambridge.arm.com> <5A9DC03B.8020201@codeaurora.org> <5AA05B57.9010005@codeaurora.org> From: Suzuki K Poulose Message-ID: Date: Mon, 19 Mar 2018 09:50:18 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <5AA05B57.9010005@codeaurora.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/03/18 21:36, Saravana Kannan wrote: > On 03/07/2018 06:59 AM, Suzuki K Poulose wrote: >> >> >> Hi Saravana, >> >> Sorry for the late response, I was out on vacation. >> >> On 05/03/18 22:10, Saravana Kannan wrote: >>> On 03/05/2018 02:59 AM, Mark Rutland wrote: >>>> On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote: >>>>> On 03/02/2018 02:42 AM, Mark Rutland wrote: >>>>>> It's important to note that the DSU PMU's event_init() ensures events >>>>>> are affine to a single CPU, and the perf core code serializes >>>>>> operations >>>>>> on those events via the context lock. >>>>> >>>>> Ah, I see that now. Thanks! >>>>> >>>>>> Therefore, two CPUs *won't* try to access the registers >>>>>> simultaneously. >>>>> >>>>> Right, and this driver seems to be going through a lot of work to >>>>> make sure >>>>> all events are read in one CPU. >>>>> >>>>> Do you even have an upstream target where there are multiple DSU's in a >>>>> system? >>>> >>>> I have no idea, though I do beleive that it's possible for a system to >>>> have multiple DSUs. >>>> >>>>> If not, we can simplify a ton of this code (no hotplug notifiers, no >>>>> migrating PMUs, no SMP calls, etc) by just adding a spinlock and >>>>> letting any >>>>> CPU read these DSU counters. >>>> >>>> Regardless of whether we allow arbitrary CPUs to read the counters, >>>> other logic still needs to be CPU affine, and we'll still need hotplug >>>> notifiers and event migration. >>> >>> If you have to support multiple DSUs in a system, then the need is >>> obvious. But if you don't have to support multiple DSU, it's not >>> obvious to me on why you still need CPU affining or hotplug notifiers. >>> Could you please provide me pointers for general understanding? >>> >> >> We need to support multiple DSUs as such configurations are possible. >> >>> >>>> I am not necessarily opposed to allowing read() calls from associated >>>> CPUs, but as before, I'll leave that to Suzuki. >> >> I am fine with reading the registers from any of the associated CPUs. >> > > If that's the case, can you please use my patch? The DSU driver is already mainline. Please feel free to send a patch with me in Cc. > And if it looks good to you, give an Ack and ask Peter to pull it in as you'd be the user? As mentioned above, when you send a patch, please do keep me in Cc, and will do the needful. Thanks Suzuki