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[209.132.180.67]) by mx.google.com with ESMTP id f33-v6si145586plb.482.2018.03.19.08.11.14; Mon, 19 Mar 2018 08:11:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=PtyhQCKF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755659AbeCSPKA (ORCPT + 99 others); Mon, 19 Mar 2018 11:10:00 -0400 Received: from mail-qk0-f182.google.com ([209.85.220.182]:33927 "EHLO mail-qk0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755406AbeCSPJz (ORCPT ); Mon, 19 Mar 2018 11:09:55 -0400 Received: by mail-qk0-f182.google.com with SMTP id z184so18658003qkc.1; Mon, 19 Mar 2018 08:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=njddE9dl6aidpVBJwAVABGrAq+/l4ifrwU1WMTFlm/k=; b=PtyhQCKF5iB/U5+Kdwusat5on9GFDsPOR3NcQy6xirU5Zhqqe3+VIsbi++0McXcwEU xOcUdlbEsAak4KpgmOFSQ0vmQdgikc0YKZvNlCxM95oey/XhtO3JPaePL5yP/CacO5lO rl7ygc9v1Ha1RhzFhwBv5pFmAlC+PVqYYtlKwVkZQuo7Bky3q0i2188VmhcO4SEHShON KEnqq2G8DxWdUFyNO6xDgsl+oZNPKtYWviJCsArysEpOCkMIXaToVwWpCKkXzR1jNyMm 8QG8C1mHKaPSqMIX/4SR+G1IxmQ0oBCDOMcrQ66wiKr7yBqWc8ngdjik4z3I5KJqRESg u6FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=njddE9dl6aidpVBJwAVABGrAq+/l4ifrwU1WMTFlm/k=; b=jWaRgdi624B4ejwhF9adnC75twJKgo5ROHcHaAch3aPlZZhrua6zV5bKmb3UwnbMaA K5jykEDClN9Gy3IqvrVms8TlahpHS71Qwl9hOvUOArJwt2ZiK4x4VLLwfdcYfSHztUtg 9HLqvyUP4yY51VyKxr+6ka3X6BCZTHPQaBz5vj2EL2BTfYjlDzn2vm1dBXAh+Yq80vFv I2R5Nzs0VEF/PJpIWrRBHG7LBBL9w4JwC8teZgpxrA1NOTNFFxQ/3jgQ3ncZi5ydrgEw GPJErN1oprkXuy/TZH0Ai94vNk6sNg6YfnHtitawf36obEK4K+rz94BLsqgV3ZoNXrke eqlA== X-Gm-Message-State: AElRT7EUC7JZks14Q3RUTbKiYGi5d3qeZ+9zHKTYM/nycjNkFM5xRWiM ZMxdNasl8oMBnvjeqZWnJb+Zdb9IfPBmcaM7sTo= X-Received: by 10.55.126.69 with SMTP id z66mr17395177qkc.218.1521472194612; Mon, 19 Mar 2018 08:09:54 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.137.74 with HTTP; Mon, 19 Mar 2018 08:09:54 -0700 (PDT) In-Reply-To: <20180319070043.GA25474@wunner.de> References: <20180310001021.6437-1-labbott@redhat.com> <20180310001021.6437-2-labbott@redhat.com> <20180317082509.GA2579@wunner.de> <20180318142327.GA23761@wunner.de> <0f17eb05-c183-bec9-0076-5ddd00d70f15@rasmusvillemoes.dk> <20180319070043.GA25474@wunner.de> From: Andy Shevchenko Date: Mon, 19 Mar 2018 17:09:54 +0200 Message-ID: Subject: Re: [PATCH 1/4] gpio: Remove VLA from gpiolib To: Lukas Wunner Cc: Rasmus Villemoes , Laura Abbott , Linus Walleij , Kees Cook , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , kernel-hardening@lists.openwall.com, Mathias Duckeck , Nandor Han , Semi Malinen , Patrice Chotard Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 19, 2018 at 9:00 AM, Lukas Wunner wrote: > On Sun, Mar 18, 2018 at 09:34:12PM +0100, Rasmus Villemoes wrote: >> On 2018-03-18 15:23, Lukas Wunner wrote: >> > Actually, scratch that. If ngpio is usually smallish, we can just >> > allocate reasonably sized space for mask and bits on the stack, >> > and fall back to the kcalloc slowpath only if chip->ngpio exceeds >> > that limit. >> Well, I'd suggest not adding that fallback code now, but simply add a >> check in gpiochip_add_data_with_key to ensure ngpio is sane (and refuse >> to register the chip otherwise), at least if we know that every >> currently supported/known chip is covered by the 256 (?). > > The number 256 was arbitrarily chosen. I really wouldn't be surprised > if gpiochips with more pins exist, but they're probably rare, so using > the slowpath seems fine, but dropping support for them completely would > be a regression. All modern Intel SoCs have GPIO count in between of ~230-380. Though, few of them are split to communities by (much) less than 256 pin in each when there is a 1:1 mapping between community and gpiochip. OTOH, the function you are fixing is most likely is not used together with the drivers for x86. -- With Best Regards, Andy Shevchenko