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received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: ztfY+ZzwGbpD5q2Z4HU8lTEkx3RohFGW56Uo/SPQ/K65UiWO8Yww4kSgLGFGcmcBulbsEgoBLKSIsB/AsfkkpqN+E0l9J5LelSpogClRkFtCNvgxD6tO+nr8OZcFFbfY+LxxdvR+PzoCSmivYnDgXCQj3JeDJhOmDqfG8V6KQlsiJeOK3yCtkmxsfSOhielyWW0MJGn8O/AsHVP3VVPBuzb/+2pU8wTGP7wsLeVhu4XduTIiKCIabcvdpE/F88yIZ0BMUC3iHKxFlLrApcI4m4fiDwy754+FOIHj78ogzbnK7+jwZYygICD1V/8tqtPom/uJLc4jh3IDW8Uu2bJv2w== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98909d8d-f14f-4aa2-c3ab-08d58db0b829 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Mar 2018 15:47:24.9042 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0998 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng [ Upstream commit cf4881c1293516c1975606e8f2af7948789168b8 ] The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3 DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE module clock). Fix this by change the clock descriptions to use the clocks of H3. Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Icenowy Zheng Signed-off-by: Chen-Yu Tsai Signed-off-by: Sasha Levin --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/cc= u-sun8i-de2.c index 5cc9d9952121..775cda4f2fd3 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -134,10 +134,10 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk= _desc =3D { }; =20 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc =3D { - .ccu_clks =3D sun8i_a83t_de2_clks, - .num_ccu_clks =3D ARRAY_SIZE(sun8i_a83t_de2_clks), + .ccu_clks =3D sun8i_h3_de2_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun8i_h3_de2_clks), =20 - .hw_clks =3D &sun8i_a83t_de2_hw_clks, + .hw_clks =3D &sun8i_h3_de2_hw_clks, =20 .resets =3D sun50i_a64_de2_resets, .num_resets =3D ARRAY_SIZE(sun50i_a64_de2_resets), --=20 2.14.1