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[209.132.180.67]) by mx.google.com with ESMTP id l13si485155pgn.346.2018.03.19.19.49.15; Mon, 19 Mar 2018 19:49:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=YZcoNPh9; dkim=pass header.i=@codeaurora.org header.s=default header.b=Xo3JxlQS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751729AbeCTCmr (ORCPT + 99 others); Mon, 19 Mar 2018 22:42:47 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41874 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751022AbeCTCml (ORCPT ); Mon, 19 Mar 2018 22:42:41 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 74D64607EB; Tue, 20 Mar 2018 02:42:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521513760; bh=Vx52RT/AwUjgCYqPTGpROGXkGCToQZe1LTchf3OkXDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YZcoNPh97eblDtiXrkXdnFOXudnjTH0+isTh3mt1O9w8T5Qu74l4wMWCRbzmmZ9z8 hiT28UimCmXOvT+1l8L+2RGlZglY1J8Ra+4lXHzq577i7bnlCvpc3AXHZGa/XEHNGI BRwbwCVkExa9hpjXuArJ/css8t+4nkpYuidhXqKg= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8F67B607EB; Tue, 20 Mar 2018 02:42:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521513759; bh=Vx52RT/AwUjgCYqPTGpROGXkGCToQZe1LTchf3OkXDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Xo3JxlQSGvLdcl+MuFhsUp0g/DQXEKpaZRmhtvPSI/wGY9me6UO+QR3oKMhDpROhN odFNEx9nj2/Ca3GZUNeUG9BU812ypsboF07uKP7zfFM2wiATZ8T1ymOvzlKfavBMYc 2O0Wj7NEy96iN79lcZSF2b26aV+gAILVqtydjEu0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8F67B607EB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Jeff Kirsher , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/17] i40e/i40evf: Eliminate duplicate barriers on weakly-ordered archs Date: Mon, 19 Mar 2018 22:42:16 -0400 Message-Id: <1521513753-7325-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521513753-7325-1-git-send-email-okaya@codeaurora.org> References: <1521513753-7325-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya Reviewed-by: Alexander Duyck --- drivers/net/ethernet/intel/i40e/i40e_txrx.c | 8 ++++---- drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index e554aa6cf..9455869 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -185,7 +185,7 @@ static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, /* Mark the data descriptor to be watched */ first->next_to_watch = tx_desc; - writel(tx_ring->next_to_use, tx_ring->tail); + writel_relaxed(tx_ring->next_to_use, tx_ring->tail); return 0; dma_fail: @@ -1375,7 +1375,7 @@ static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) * such as IA-64). */ wmb(); - writel(val, rx_ring->tail); + writel_relaxed(val, rx_ring->tail); } /** @@ -2258,7 +2258,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) */ wmb(); - writel(xdp_ring->next_to_use, xdp_ring->tail); + writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); } rx_ring->skb = skb; @@ -3286,7 +3286,7 @@ static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c index 357d605..56eea20 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c @@ -667,7 +667,7 @@ static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) * such as IA-64). */ wmb(); - writel(val, rx_ring->tail); + writel_relaxed(val, rx_ring->tail); } /** @@ -2243,7 +2243,7 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems -- 2.7.4