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[209.132.180.67]) by mx.google.com with ESMTP id d21-v6si891515pll.559.2018.03.19.23.08.49; Mon, 19 Mar 2018 23:09:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751587AbeCTGH7 (ORCPT + 99 others); Tue, 20 Mar 2018 02:07:59 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:50970 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751269AbeCTGH4 (ORCPT ); Tue, 20 Mar 2018 02:07:56 -0400 X-UUID: b6b4201d53734789b1c996bce842dda7-20180320 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1301728245; Tue, 20 Mar 2018 14:07:49 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 20 Mar 2018 14:07:47 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 20 Mar 2018 14:07:47 +0800 Message-ID: <1521526068.13313.8.camel@mtksdaap41> Subject: Re: [PATCH v2 0/5] update Mediatek MT2712 clock and scpsys support From: Weiyi Lu To: Matthias Brugger , Stephen Boyd CC: Mike Turquette , Rob Herring , James Liao , Fan Chen , , , , , , Date: Tue, 20 Mar 2018 14:07:48 +0800 In-Reply-To: <20180312070342.4335-1-weiyi.lu@mediatek.com> References: <20180312070342.4335-1-weiyi.lu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2018-03-12 at 15:03 +0800, Weiyi Lu wrote: > This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2) and clock control (PATCH 3-5). > Basically, all changes are for the ECO design change of MT2712. > > changes since v1: > - Avoid renumbering clocks. Append new clocks at the bottom of each own subsystem. > Hi Matthias & Stephen, Sorry to bother. Just saw patch 1/2 are already pushed to v4.16-next-soc and patch 3/5 are applied onto clk-next. What about the patch 4(arm64: dts: add clock device nodes of MT2712). Does there any problem remain or it cause some problems? Many thanks. > Weiyi Lu (5): > dt-bindings: soc: update MT2712 power dt-bindings > soc: mediatek: update power domain data of MT2712 > dt-bindings: clock: add clocks for MT2712 > arm64: dts: add clock device nodes of MT2712 > clk: mediatek: update clock driver of MT2712 > > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 +++++++++++++ > drivers/clk/mediatek/clk-mt2712.c | 69 ++++++++++++++++++++++++------- > drivers/soc/mediatek/mtk-scpsys.c | 42 ++++++++++++++++++- > include/dt-bindings/clock/mt2712-clk.h | 12 +++++- > include/dt-bindings/power/mt2712-power.h | 3 ++ > 5 files changed, 136 insertions(+), 18 deletions(-) >