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[209.132.180.67]) by mx.google.com with ESMTP id g1-v6si1665097plp.327.2018.03.20.06.11.14; Tue, 20 Mar 2018 06:11:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753372AbeCTNIP (ORCPT + 99 others); Tue, 20 Mar 2018 09:08:15 -0400 Received: from mail.bootlin.com ([62.4.15.54]:42723 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753091AbeCTNIN (ORCPT ); Tue, 20 Mar 2018 09:08:13 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 8B6D920879; Tue, 20 Mar 2018 14:08:11 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (unknown [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 49777203A2; Tue, 20 Mar 2018 14:08:01 +0100 (CET) From: Alexandre Belloni To: James Hogan , Ralf Baechle Cc: Allan Nielsen , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni Subject: [PATCH v6 0/6] MIPS: add support for Microsemi MIPS SoCs Date: Tue, 20 Mar 2018 14:07:55 +0100 Message-Id: <20180320130801.9247-1-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.16.2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This patch series adds initial support for the Microsemi MIPS SoCs. It is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514). Changes in v6: - Fixup SPDX identifiers - remove unit-address for cpuintc - add unit-address for ahb - remove CONFIG_32BIT requirement (implied by CONFIG_CPU_MIPS32_R2) - Add TLB entry lookup provided by James - Readd vendor prefix addition Alexandre Belloni (6): dt-bindings: Add vendor prefix for Microsemi Corporation dt-bindings: mips: Add bindings for Microsemi SoCs MIPS: mscc: add ocelot dtsi MIPS: mscc: add ocelot PCB123 device tree MIPS: generic: Add support for Microsemi Ocelot MAINTAINERS: Add entry for Microsemi MIPS SoCs Documentation/devicetree/bindings/mips/mscc.txt | 43 ++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 9 ++ arch/mips/Makefile | 4 + arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/mscc/Makefile | 3 + arch/mips/boot/dts/mscc/ocelot.dtsi | 117 +++++++++++++++++++++ arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 +++++ arch/mips/configs/generic/board-ocelot.config | 35 ++++++ arch/mips/generic/Kconfig | 16 +++ arch/mips/generic/Makefile | 1 + arch/mips/generic/board-ocelot.c | 78 ++++++++++++++ 12 files changed, 335 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt create mode 100644 arch/mips/boot/dts/mscc/Makefile create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts create mode 100644 arch/mips/configs/generic/board-ocelot.config create mode 100644 arch/mips/generic/board-ocelot.c -- 2.16.2