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[209.132.180.67]) by mx.google.com with ESMTP id l128si1279964pgl.248.2018.03.20.08.07.21; Tue, 20 Mar 2018 08:07:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751553AbeCTPFt (ORCPT + 99 others); Tue, 20 Mar 2018 11:05:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:60958 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750991AbeCTPFr (ORCPT ); Tue, 20 Mar 2018 11:05:47 -0400 Received: from mail-it0-f42.google.com (mail-it0-f42.google.com [209.85.214.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5A9CF21770 for ; Tue, 20 Mar 2018 15:05:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A9CF21770 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=luto@kernel.org Received: by mail-it0-f42.google.com with SMTP id z7-v6so13013221iti.1 for ; Tue, 20 Mar 2018 08:05:47 -0700 (PDT) X-Gm-Message-State: AElRT7G26+ak5OYeZLWby7rIeAzHtP9QYnRkTW2mMxJXStnUMbhezr9I PzfBH10TlSG4nisB+hQz53DFBnEFKGt96x+BrQ/3lA== X-Received: by 2002:a24:b841:: with SMTP id m62-v6mr40333ite.55.1521558346799; Tue, 20 Mar 2018 08:05:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.2.137.70 with HTTP; Tue, 20 Mar 2018 08:05:26 -0700 (PDT) In-Reply-To: <1521481767-22113-1-git-send-email-chang.seok.bae@intel.com> References: <1521481767-22113-1-git-send-email-chang.seok.bae@intel.com> From: Andy Lutomirski Date: Tue, 20 Mar 2018 15:05:26 +0000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/15] x86: Enable FSGSBASE instructions To: "Chang S. Bae" Cc: X86 ML , Andrew Lutomirski , Andi Kleen , "H. Peter Anvin" , "Metzger, Markus T" , Tony Luck , "Ravi V. Shankar" , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 19, 2018 at 5:49 PM, Chang S. Bae wrote: > FSGSBASE is 64-bit instruction set to allow read/write > FS/GS base from any privilege. As introduced from > Ivybridge, enabling effort has been revolving quite long > [2,3,4] for various reasons. After extended discussions [1], > this patchset is proposed to introduce new ABIs of > customizing FS/GS base (separate from its selector). > > FSGSBASE-enabled VM can be located on hosts with > either HW virtualization or SW emulation. KVM advertises > FSGSBASE when physical CPU has and emulation is > supported in QEMU/TCG [5]. In a pool of mixed systems, VMM > may disable FSGSBASE for seamless VM migrations [6]. > > A couple of major benefits are expected. Kernel will have > performance improvement in context switch by skipping MSR > write for GS base. User-level programs (such as JAVA-based) > benefit from avoiding system calls to edit FS/GS base. Can you describe what changed since the last submission? It looks like a lot has changed and this series is much more complicated and much more fragile than it used to be. Why?