Received: by 10.213.65.68 with SMTP id h4csp864604imn; Tue, 20 Mar 2018 18:12:24 -0700 (PDT) X-Google-Smtp-Source: AG47ELv+0vJoPe2sEzFYSnaVY+1thh2PNJhYbDgpmxKHy53fS6efpGkib4HCNlvtB4GNoUgvVL5v X-Received: by 10.98.39.7 with SMTP id n7mr13590910pfn.161.1521594744152; Tue, 20 Mar 2018 18:12:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521594744; cv=none; d=google.com; s=arc-20160816; b=r26XxT997CZpszF4ASp079GZ2FY0dGPWy8O3T8DFYJKfxTVyBdeJIupJmtRWMDEZrv A5dcLcf2b9UL1cHyo5pxSF+N4Ywuaoq5tcjEJRC5XTc0Q4Vnb0lkFNRhtucJ4yVQan4X qVcqCflhojIaPKxv7buB1+EywOav1tc4b/CBv8u8tdIzeoMZQx5+FSYf2m52v2zD1IHN DU3bSpmnCR05RvdkDGuOJo5pcjC/ALwxOxMriu0BOl8d79u2GjxJQeCJjHTWNZ1dkwlb 3U9tOzTRqATiPj3eXoYOhRZb1b2NwAc356/63Tlnkxvc8m0koIw6ozDBsMmGNOfNGces jFXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VdUK/6XLLn6Ib1AaKrH6ws6iI/7T6eBueweJlUwddn8=; b=WuPuNiMB4E7KucUpaLlgLQ1UcU40BiN+KFwtp0DUPQ0hf6LfaD2KsGh8lQNQ3zjlfm 3pMgGLpTct6KEFPGy3ubtmEGjcvswgoZ1tf6rZmoJM+54lagcdJd6sDh8iR4YK5RKA76 jH6WFWZMfM3IjBAzn9WSLXz+pJjUKnIvItLK9lGl+YlW3ey+sq3QuhXk08GxqrP8VtRm /H6DJH502m+CEpH+B+FpXHdx+HG+OAFTyIPJ9awroyAYKVvBhk83BsrNdnXSy7ovkJWT 99VGMj7ojrTQ3GYOr9RZqiWu3PANMvgDA6yAbP/2t2hBZewgVXz5lo6ZcWfLIx5HCd7M e6JA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x7si912817pgv.796.2018.03.20.18.12.09; Tue, 20 Mar 2018 18:12:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751688AbeCUBLL (ORCPT + 99 others); Tue, 20 Mar 2018 21:11:11 -0400 Received: from mga09.intel.com ([134.134.136.24]:19664 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751557AbeCUBLH (ORCPT ); Tue, 20 Mar 2018 21:11:07 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Mar 2018 18:11:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,338,1517904000"; d="scan'208";a="39779343" Received: from vmm.bj.intel.com ([10.238.135.172]) by fmsmga001.fm.intel.com with ESMTP; 20 Mar 2018 18:11:04 -0700 From: Luwei Kang To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, joro@8bytes.org, Chao Peng , Luwei Kang Subject: [PATCH v6 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function Date: Tue, 20 Mar 2018 19:21:49 +0800 Message-Id: <1521544918-31084-3-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521544918-31084-1-git-send-email-luwei.kang@intel.com> References: <1521544918-31084-1-git-send-email-luwei.kang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chao Peng Change pt_cap_get() to a public function so that KVM can access it. Introduce new capablility PT_CAP_output_subsys to support of output to Trace Transport subsystem. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang --- arch/x86/events/intel/pt.c | 4 +++- arch/x86/events/intel/pt.h | 21 --------------------- arch/x86/include/asm/intel_pt.h | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 6d6dd4f..d89dd8c 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -68,6 +68,7 @@ PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)), PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)), PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)), + PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)), PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)), PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3), PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000), @@ -75,7 +76,7 @@ PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000), }; -static u32 pt_cap_get(enum pt_capabilities cap) +u32 pt_cap_get(enum pt_capabilities cap) { struct pt_cap_desc *cd = &pt_caps[cap]; u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; @@ -83,6 +84,7 @@ static u32 pt_cap_get(enum pt_capabilities cap) return (c & cd->mask) >> shift; } +EXPORT_SYMBOL_GPL(pt_cap_get); static ssize_t pt_cap_show(struct device *cdev, struct device_attribute *attr, diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h index 0050ca1..269e15a 100644 --- a/arch/x86/events/intel/pt.h +++ b/arch/x86/events/intel/pt.h @@ -45,30 +45,9 @@ struct topa_entry { u64 rsvd4 : 16; }; -#define PT_CPUID_LEAVES 2 -#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ - /* TSC to Core Crystal Clock Ratio */ #define CPUID_TSC_LEAF 0x15 -enum pt_capabilities { - PT_CAP_max_subleaf = 0, - PT_CAP_cr3_filtering, - PT_CAP_psb_cyc, - PT_CAP_ip_filtering, - PT_CAP_mtc, - PT_CAP_ptwrite, - PT_CAP_power_event_trace, - PT_CAP_topa_output, - PT_CAP_topa_multiple_entries, - PT_CAP_single_range_output, - PT_CAP_payloads_lip, - PT_CAP_num_address_ranges, - PT_CAP_mtc_periods, - PT_CAP_cycle_thresholds, - PT_CAP_psb_periods, -}; - struct pt_pmu { struct pmu pmu; u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h index b523f51..2de4db0 100644 --- a/arch/x86/include/asm/intel_pt.h +++ b/arch/x86/include/asm/intel_pt.h @@ -2,10 +2,34 @@ #ifndef _ASM_X86_INTEL_PT_H #define _ASM_X86_INTEL_PT_H +#define PT_CPUID_LEAVES 2 +#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ + +enum pt_capabilities { + PT_CAP_max_subleaf = 0, + PT_CAP_cr3_filtering, + PT_CAP_psb_cyc, + PT_CAP_ip_filtering, + PT_CAP_mtc, + PT_CAP_ptwrite, + PT_CAP_power_event_trace, + PT_CAP_topa_output, + PT_CAP_topa_multiple_entries, + PT_CAP_single_range_output, + PT_CAP_output_subsys, + PT_CAP_payloads_lip, + PT_CAP_num_address_ranges, + PT_CAP_mtc_periods, + PT_CAP_cycle_thresholds, + PT_CAP_psb_periods, +}; + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) void cpu_emergency_stop_pt(void); +extern u32 pt_cap_get(enum pt_capabilities cap); #else static inline void cpu_emergency_stop_pt(void) {} +static inline u32 pt_cap_get(enum pt_capabilities cap) { return 0; } #endif #endif /* _ASM_X86_INTEL_PT_H */ -- 1.8.3.1