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[209.132.180.67]) by mx.google.com with ESMTP id s8-v6si4473064plk.550.2018.03.21.08.33.34; Wed, 21 Mar 2018 08:33:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752759AbeCUPa5 (ORCPT + 99 others); Wed, 21 Mar 2018 11:30:57 -0400 Received: from mail.bootlin.com ([62.4.15.54]:47248 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752315AbeCUPas (ORCPT ); Wed, 21 Mar 2018 11:30:48 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 21E382055E; Wed, 21 Mar 2018 16:30:46 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.bootlin.com (Postfix) with ESMTPSA id B309A20858; Wed, 21 Mar 2018 16:30:45 +0100 (CET) From: Paul Kocialkowski To: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Cc: Maxime Ripard , David Airlie , Chen-Yu Tsai , Daniel Vetter , Gustavo Padovan , Sean Paul , Paul Kocialkowski Subject: [PATCH 02/10] drm/sun4i: Disable YUV channel when using the frontend and set interlace Date: Wed, 21 Mar 2018 16:28:56 +0100 Message-Id: <20180321152904.22411-3-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180321152904.22411-1-paul.kocialkowski@bootlin.com> References: <20180321152904.22411-1-paul.kocialkowski@bootlin.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The YUV channel was only disabled in sun4i_backend_update_layer_formats, which is not called when the frontend is selected. Thus, creating a layer with a YUV format handled by the backend and then switching to a format that requires the frontend would keep the YUV channel enabled for the layer. This explicitly disables the YUV channel for the layer when using the frontend as well. It also sets the relevant interlace bit, which was missing in the frontend path as well. Signed-off-by: Paul Kocialkowski --- drivers/gpu/drm/sun4i/sun4i_backend.c | 17 ++++++++++++++++- drivers/gpu/drm/sun4i/sun4i_backend.h | 3 ++- drivers/gpu/drm/sun4i/sun4i_layer.c | 2 +- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index e07a33adc51d..b98dafda52f8 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -294,8 +294,10 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, } int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, - int layer, uint32_t fmt) + int layer, struct drm_plane *plane, + uint32_t fmt) { + bool interlaced = false; u32 val; int ret; @@ -305,11 +307,24 @@ int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, return ret; } + /* Clear the YUV mode */ + regmap_update_bits(backend->engine.regs, + SUN4I_BACKEND_ATTCTL_REG0(layer), + SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); + regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN, SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN); + if (plane->state->crtc) + interlaced = plane->state->crtc->state->adjusted_mode.flags + & DRM_MODE_FLAG_INTERLACE; + + regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, + SUN4I_BACKEND_MODCTL_ITLMOD_EN, + interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); + regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG1(layer), SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h index 7ae0f0ffec8c..cb6df2b690c0 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.h +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h @@ -201,7 +201,8 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, int layer, struct drm_plane *plane); int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, - int layer, uint32_t in_fmt); + int layer, struct drm_plane *plane, + uint32_t fmt); int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, struct drm_plane *plane); void sun4i_backend_disable_layer_frontend(struct sun4i_backend *backend, diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 224bb1811e0a..eb93df445a10 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -101,7 +101,7 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, sun4i_frontend_update_buffer(frontend, plane); sun4i_frontend_update_formats(frontend, plane, DRM_FORMAT_ARGB8888); - sun4i_backend_update_layer_frontend(backend, layer->id, + sun4i_backend_update_layer_frontend(backend, layer->id, plane, DRM_FORMAT_ARGB8888); sun4i_frontend_enable(frontend); } else { -- 2.16.2