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[209.132.180.67]) by mx.google.com with ESMTP id 11si1668432pfu.71.2018.03.21.10.46.55; Wed, 21 Mar 2018 10:47:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=k8pkQipL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752497AbeCURpd (ORCPT + 99 others); Wed, 21 Mar 2018 13:45:33 -0400 Received: from mail-qt0-f181.google.com ([209.85.216.181]:33388 "EHLO mail-qt0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752416AbeCURpa (ORCPT ); Wed, 21 Mar 2018 13:45:30 -0400 Received: by mail-qt0-f181.google.com with SMTP id i8so6147320qtj.0; Wed, 21 Mar 2018 10:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=2sSvDYdBs2f5hJjaIgoLg4nWKQiwKnReH+lgp70N6z8=; b=k8pkQipLQjHmWQfY+AD6nRP/sp7bXWSK/04LCBFnPVc8n9PHt3gR22NOWL0pCi3Ebp 88ITJi1shLgmzUU7Ybj2D1gzDiEj8U8Ql/Th1NgjWe3Ckjq4CJ64nUCx+oWldm4IGp3Y oK2TIcveK4moS9dx+YGpgJNk9E9/D54mUY9rhIqRxNR3FboBfYcOAMBhclPPGVbdpzE2 x5MoPumjxwrL2T2jjJ4wTUxVYFBrgSnsqKtgYdfpQNBAvMYOzmV4tperxxINxaDxk0WD fUEU+UgOG6m9lzKjG5vObcReJDzYC5l3iXOqbRxQSd8QN/yhmgOD9lZQkj0LGAYExq8/ 12BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=2sSvDYdBs2f5hJjaIgoLg4nWKQiwKnReH+lgp70N6z8=; b=Dc9qVTaNSKzs5uCEdl0o5d6pdwb/Shte6ONHxroLRZe2FeRYBLPMnwG83a3GWWi1DX 1Ac//j7CC1XNcCsSItTvLaUkT5zXXKo6d7htcc4+PdtueAjkMGImtCzr3nwjh9BX1rJL Vb6oDXIN5TihvS05NO5210WI9nsSxuV45GAxM5ceh2GovDVG5Jv9fT0X97xvmP2y6GWs KS3ymfiUC2ZtkxaNMGnIYQvetxc+Bn5M422FBRC1SDC66k+Dr9rzM6StONv0Jnmkz96W PX9/JrCmIpDsxZzw/G+2c6F21Q6BghCmfeL6FXM7C0tOd33r/Bi82aQOHbQuwrix2Hon hweQ== X-Gm-Message-State: AElRT7F41hg3eAaAogKOpuhdpkWjGyWSagqGrehKm1uBLKQoxcdsRFi3 YbeSfPnYZ3taq+pNiFeip5aYUJpb7UVY4kEeu74= X-Received: by 10.200.26.69 with SMTP id q5mr29902405qtk.174.1521654329916; Wed, 21 Mar 2018 10:45:29 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.137.74 with HTTP; Wed, 21 Mar 2018 10:45:29 -0700 (PDT) In-Reply-To: <6ca4bf0ed930c057bdbcd07bab34ed0a474dd78d.1521301345.git.vilhelm.gray@gmail.com> References: <6ca4bf0ed930c057bdbcd07bab34ed0a474dd78d.1521301345.git.vilhelm.gray@gmail.com> From: Andy Shevchenko Date: Wed, 21 Mar 2018 19:45:29 +0200 Message-ID: Subject: Re: [PATCH v3 3/8] gpio: pci-idio-16: Implement get_multiple callback To: William Breathitt Gray Cc: Linus Walleij , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , linux-iio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Mar 17, 2018 at 5:50 PM, William Breathitt Gray wrote: > The ACCES I/O PCI-IDIO-16 series of devices provides 16 > optically-isolated digital inputs accessed via two 8-bit ports. Since > eight input lines are acquired on a single port input read, the > PCI-IDIO-16 GPIO driver may improve multiple input reads by utilizing a > get_multiple callback. This patch implements the > idio_16_gpio_get_multiple function which serves as the respective > get_multiple callback. > +static int idio_16_gpio_get_multiple(struct gpio_chip *chip, > + unsigned long *mask, unsigned long *bits) > +{ > + struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip); > + size_t i; > + const unsigned int gpio_reg_size = 8; > + unsigned int bits_offset; > + size_t word_index; > + unsigned int word_offset; > + unsigned long word_mask; > + const unsigned long port_mask = GENMASK(gpio_reg_size, 0); gpio_reg_size - 1? Though I would prefer not to have that variable at all, just use 8 or 7 respectively. > + unsigned long port_state; > + u8 __iomem ports[] = { > + idio16gpio->reg->out0_7, idio16gpio->reg->out8_15, > + idio16gpio->reg->in0_7, idio16gpio->reg->in8_15 I would leave comma even here. > + }; > + /* get bits are evaluated a gpio port register at a time */ > + for (i = 0; i < ARRAY_SIZE(ports); i++) { > + /* gpio offset in bits array */ > + bits_offset = i * gpio_reg_size; > + > + /* word index for bits array */ > + word_index = BIT_WORD(bits_offset); > + > + /* gpio offset within current word of bits array */ > + word_offset = bits_offset % BITS_PER_LONG; > + > + /* mask of get bits for current gpio within current word */ > + word_mask = mask[word_index] & (port_mask << word_offset); > + if (!word_mask) { > + /* no get bits in this port so skip to next one */ > + continue; > + } > + > + /* read bits from current gpio port */ > + port_state = ioread8(ports + i); > + > + /* store acquired bits at respective bits array offset */ > + bits[word_index] |= port_state << word_offset; > + } I would propose to do other way around, i.e. read all ports to the bitmap array and call bitmap_and() after. Further optimization can be something like introduction of generic bitmap_copy_uXX_off(unsigned long *dst, u8 src, unsigned int offset); It can be done using macros, though it's another story not quite related to the topic. > +} -- With Best Regards, Andy Shevchenko