Received: by 10.213.65.68 with SMTP id h4csp4275imn; Wed, 21 Mar 2018 11:01:20 -0700 (PDT) X-Google-Smtp-Source: AG47ELvxaRtutdK4E3KckAWmqn0gbsTHYY46XIIYCP0ZsKRx/Ind2TSf5ZWK6zfunlwyMNHCPq8r X-Received: by 2002:a17:902:52c7:: with SMTP id a65-v6mr21651929pli.249.1521655280358; Wed, 21 Mar 2018 11:01:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521655280; cv=none; d=google.com; s=arc-20160816; b=oRcKJmQ0M9zQLnuR1/UoylayX9xO8xXxJ7OGlc08S4E/9voQOoAaMHLs8gGXYCPW5t cMtK+davMDa5oFAtcH/Vt/LktqaMJsjXo+Stb3QbCrz6/4gBs6EQOI0efBSGKozjBASg fLde31is/xTzlUKwkrdQEoPJQajyuX/R81lOQkhH7u97E/PNBgUbf2lw4Gw4XZKsxr8l 7WQSzO4AJIv4DG02TiDSHV7c66gO+wOle6yt4AzCm98TG0XVdSFshPwBy8gKJr5DK+sM +EtOnlW+jc/gCBOAkJx1IJ/h+hvtNFS/SGjjBd5cWKqqi9XN8VbfnU/YhI/Ind9xOmHi 6n2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:date:cc:to:from:subject :message-id:arc-authentication-results; bh=az4MtVBIFXgs/9PIsPtgR6sWZHgqWmT3p/wi+SFFQ6E=; b=Jei+atPAFBtzlsiwqzKN03e4SKbQwIb1nxqyBWZzqXQ9y24tI9pD2Y7zwZ1V6B11SJ UvOUofcGN/tUopMEMKZUqFtsZj1U6JfZxkpCXnRrYYnU36GFYZZDatdpGLaZjR2P3DZt cZVNnib3qqSW09zRiuofPSwooa7g/A2Xiy+n2LJRtjPtHbCSffladd4d6e4oNcxXHN5I r9+b6uxKxn2l6v0mlRZ1gDomWdqGs2wjjBwOSfc+sJeworw8/r1dzFVQvUvjaRAkVEpC 8HsxwzQI0JU9ejVkEFqAdqs2N1F3wFhWV8gOxgSC2MlS6SQzyffX+7oByTW6AOjvze1B AulA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3-v6si4274322plc.700.2018.03.21.11.00.56; Wed, 21 Mar 2018 11:01:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752561AbeCUR7P (ORCPT + 99 others); Wed, 21 Mar 2018 13:59:15 -0400 Received: from mga05.intel.com ([192.55.52.43]:63363 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752432AbeCUR7O (ORCPT ); Wed, 21 Mar 2018 13:59:14 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2018 10:59:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,340,1517904000"; d="scan'208";a="30043316" Received: from smile.fi.intel.com (HELO smile) ([10.237.72.86]) by fmsmga002.fm.intel.com with ESMTP; 21 Mar 2018 10:59:10 -0700 Message-ID: <1521655150.23017.79.camel@linux.intel.com> Subject: Re: [PATCH v3 2/3] gpiolib: Support 'gpio-reserved-ranges' property From: Andy Shevchenko To: Stephen Boyd , Linus Walleij Cc: Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org Date: Wed, 21 Mar 2018 19:59:10 +0200 In-Reply-To: <20180321165848.89751-3-swboyd@chromium.org> References: <20180321165848.89751-1-swboyd@chromium.org> <20180321165848.89751-3-swboyd@chromium.org> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.5-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2018-03-21 at 09:58 -0700, Stephen Boyd wrote: > From: Stephen Boyd > > Some qcom platforms make some GPIOs or pins unavailable for use by > non-secure operating systems, and thus reading or writing the > registers > for those pins will cause access control issues. Add support for a DT > property to describe the set of GPIOs that are available for use so > that > higher level OSes are able to know what pins to avoid reading/writing. > Non-DT platforms can add support by directly updating the > chip->valid_mask. > Signed-off-by: Stephen Boyd > Signed-off-by: Stephen Boyd Hmm... > + gpiochip->valid_mask = kcalloc(BITS_TO_LONGS(gpiochip- > >ngpio), > + sizeof(long), GFP_KERNEL); Just noticed that kcalloc is superfluous here. kmalloc_array() would be enough. > + if (!gpiochip->valid_mask) > + return -ENOMEM; > + > + /* Assume by default all GPIOs are valid */ > + bitmap_fill(gpiochip->valid_mask, gpiochip->ngpio); -- Andy Shevchenko Intel Finland Oy