Received: by 10.213.65.68 with SMTP id h4csp317506imn; Wed, 21 Mar 2018 20:00:55 -0700 (PDT) X-Google-Smtp-Source: AG47ELvwBImNGIgWWJ6DeFBzIne4xoZsB4C+gCuwi6b+XXoLJ2ybwuvw/3BhXieNvrTxQ6XFCH7r X-Received: by 10.167.129.152 with SMTP id g24mr262023pfi.117.1521687655738; Wed, 21 Mar 2018 20:00:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521687655; cv=none; d=google.com; s=arc-20160816; b=LJUGVkjYorJXqx4plJdi8UYM/mUbKH9zRr72K1x5lKzC37uSQH8tL58z5uaaa85dMs NtedluZS+rlF1qMdQisEiz5Xz/Xbtc9doK6hSmfGCU45KdnqkFZ5PUm3OMYnFHNdoJ4B ZfO+APfdD8m7q/pBhCqYIEoET2yzU67AlVv6XkMdmlYzHQHcU6ORLlfqaoboDJ8YfR25 C7IlcHRef9gQ0BqDDiiBKBIATo2k04KWEL1dBBLsTJpjEtNwXVapuWNxYPQ/vOD4G6xC RCJwN+L5dTXHW+W1lSQM1fbRIPn+Yy89GLF4+zhWaUkz7Wq35nupbU3Jv+RYz6iKNskf dqMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wm/7KbzfL3VedC+gcgSIStbrpd2IKqkAYf0vdKvVexs=; b=sm+woBcu0a5+Ze0KmZ13Ju+h3ok7XnIDT4Mq33LjBrxH7lTZv7bX2grGl1CS198Ipb f47EEZlVRcKWtMUnIOPzXlvJL/NvmiMxynA4wVRLdg4wLTK3PWK9XXERnZqA0ixLLEa6 3Mqm72AapP8Wd3qgK0YiBi3V1S6EgXo8yjHootLIuZHDkpGzHlAzWw/rrDyJhmSZDhkH xbN2u1D+kLPn7cAVWWzDQVjLrl/L5AL64qt07whNRBHSW7BvYW3MZ9Clw8+ZCF99ySIG f1QblMjVyZEl7cGJHhgW6iJ23hzYJLuAycXsiSYPpU1eHVsb7anEa+oFdYRn1ULzqtWL DUgg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17-v6si5778910plr.310.2018.03.21.20.00.29; Wed, 21 Mar 2018 20:00:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751959AbeCVC66 (ORCPT + 99 others); Wed, 21 Mar 2018 22:58:58 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:21635 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751625AbeCVC6z (ORCPT ); Wed, 21 Mar 2018 22:58:55 -0400 X-UUID: ff44d4a2c5ea42da9b64b6648171d7e7-20180322 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1352142001; Thu, 22 Mar 2018 10:58:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 22 Mar 2018 10:58:48 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 22 Mar 2018 10:58:48 +0800 From: Zhiyong Tao To: , , , CC: , , , , , , , , , , , , , Zhiyong Tao Subject: [PATCH v4 2/5] arm64: dts: mt2712: add pintcrl device node. Date: Thu, 22 Mar 2018 10:58:40 +0800 Message-ID: <1521687523-1604-3-git-send-email-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521687523-1604-1-git-send-email-zhiyong.tao@mediatek.com> References: <1521687523-1604-1-git-send-email-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds pintcrl device node for mt2712. Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index d7688bc..fb3b051 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include "mt2712-pinfunc.h" / { compatible = "mediatek,mt2712"; @@ -258,6 +259,23 @@ #clock-cells = <1>; }; + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt2712-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt2712-scpsys", "syscon"; #power-domain-cells = <1>; -- 1.9.1