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[209.132.180.67]) by mx.google.com with ESMTP id x61-v6si3166291plb.213.2018.03.21.23.10.50; Wed, 21 Mar 2018 23:11:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752229AbeCVGJv convert rfc822-to-8bit (ORCPT + 99 others); Thu, 22 Mar 2018 02:09:51 -0400 Received: from hermes.aosc.io ([199.195.250.187]:40005 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752004AbeCVGJs (ORCPT ); Thu, 22 Mar 2018 02:09:48 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 0B9B159DFF; Thu, 22 Mar 2018 06:09:39 +0000 (UTC) Date: Thu, 22 Mar 2018 14:08:43 +0800 In-Reply-To: <2866474.lRHIcLtROC@jernej-laptop> References: <20180316175354.21437-1-icenowy@aosc.io> <20180320184646.dynqv6qubzabroe4@flea> <2866474.lRHIcLtROC@jernej-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Subject: Re: [linux-sunxi] Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus To: jernej.skrabec@siol.net, =?UTF-8?Q?Jernej_=C5=A0krabec?= , linux-sunxi@googlegroups.com CC: Maxime Ripard , Rob Herring , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org From: Icenowy Zheng Message-ID: <9520BDDE-BFE3-4220-B48D-01A00CFA94DE@aosc.io> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" 写到: >Hi all, > >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a): >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard > >写到: >> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote: >> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 >SoC >> > >> >to >> > >> >> be claimed, otherwise the whole DE2 space is inaccessible. >> >> >> >> Add a device tree binding of the DE2 part as a sub-bus. >> > >> >Where did you get the info that it was a bus? >> >> There's no direct evidence, just some guess. >> >> The DE2 is a whole part that is just allocated a memory >> space at the user manual, and the SRAM controls the >> access to all modules in the DE2. >> >> So it might be a bus. >> >> Implement it as a bus is a clear representation on A64. > >Since there is already syscon for same mmio region, we migh as well use >it >when loading ccu-sun8i-de2 driver on A64. > >Other options, like SRAM driver or bus driver, might better represent >HW, but I think the device tree should properly represent the HW, it's a basic requirment. >then we would have two DT nodes covering same mmio region, which I >think is >not really acceptable. It's acceptable, and DE2 is not the only user of SRAM controller so far. VE will also need a SRAM region to be claimed. > >Any suggestions? > >BTW, H6 has same design in this regard. > >Best regards, >Jernej