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[209.132.180.67]) by mx.google.com with ESMTP id w4si4200515pgo.305.2018.03.22.04.17.17; Thu, 22 Mar 2018 04:17:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753851AbeCVK3L convert rfc822-to-8bit (ORCPT + 99 others); Thu, 22 Mar 2018 06:29:11 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14813 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752087AbeCVK3I (ORCPT ); Thu, 22 Mar 2018 06:29:08 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 22 Mar 2018 03:29:17 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 22 Mar 2018 03:29:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 22 Mar 2018 03:29:03 -0700 Received: from DRUKMAIL101.nvidia.com (10.25.59.19) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 22 Mar 2018 10:29:04 +0000 Received: from BGMAIL101.nvidia.com (10.25.59.10) by drukmail101.nvidia.com (10.25.59.19) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 22 Mar 2018 10:28:59 +0000 Received: from BGMAIL101.nvidia.com ([::1]) by bgmail101.nvidia.com ([fe80::f084:44ac:7596:f4bc%19]) with mapi id 15.00.1347.000; Thu, 22 Mar 2018 10:28:59 +0000 From: Aniruddha Banerjee To: Marc Zyngier CC: "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , Jonathan Hunter , Stephen Warren , Thierry Reding , Vipin Kumar Subject: [RFC PATCH] irqchip: arm-gic: take gic_lock when updating irq type Thread-Topic: [RFC PATCH] irqchip: arm-gic: take gic_lock when updating irq type Thread-Index: AdPBxF2SqE+GlSbOTIC23ydnb4Rn2w== Date: Thu, 22 Mar 2018 10:28:59 +0000 Message-ID: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.24.44.47] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The kernel documentation states that the irq-chip driver should handle the locking of the irq-chip registers. In the irq-gic, the accesses to the irqchip are seemingly not protected and multiple writes to SPIs from different irq descriptors do RMW requests without taking the irq-chip lock. When multiple irqs call the request_irq at the same time, there can be a simultaneous write at the gic distributor, leading to a race. Acquire the irq_controller lock when the irq_type is updated. This patch is only for GICv2; however, I have noticed a similar implementation in GICv3. This patch is sent as an RFC in case I am missing anything. Signed-off-by: Aniruddha Banerjee --- drivers/irqchip/irq-gic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4c797b43614d..61380f5a2254 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -67,6 +67,8 @@ static void gic_check_cpu_features(void) #define gic_check_cpu_features() do { } while(0) #endif +static DEFINE_RAW_SPINLOCK(irq_controller_lock); + union gic_base { void __iomem *common_base; void __percpu * __iomem *percpu_base; @@ -529,6 +531,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); unsigned int gicirq = gic_irq(d); + int ret; /* Interrupt configuration for SGIs can't be changed */ if (gicirq < 16) @@ -539,7 +542,11 @@ static int gic_set_type(struct irq_data *d, unsigned int type) type != IRQ_TYPE_EDGE_RISING) return -EINVAL; - return gic_configure_irq(gicirq, type, base, NULL); + raw_spin_lock(&irq_controller_lock); + ret = gic_configure_irq(gicirq, type, base, NULL); + raw_spin_unlock(&irq_controller_lock); + + return ret; } static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) -- 2.15.1