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[209.132.180.67]) by mx.google.com with ESMTP id a63-v6si7804427pla.718.2018.03.22.23.13.03; Thu, 22 Mar 2018 23:13:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=pGX+mPUD; dkim=pass header.i=@codeaurora.org header.s=default header.b=TD941cSH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751797AbeCWGMB (ORCPT + 99 others); Fri, 23 Mar 2018 02:12:01 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41914 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751745AbeCWGL5 (ORCPT ); Fri, 23 Mar 2018 02:11:57 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 01620607EB; Fri, 23 Mar 2018 06:11:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521785517; bh=zW8gwN2xBaQ+o40Oh619Mh7SE0QP+OAoyw9M4j7ZNZ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pGX+mPUDdAB2ss5K4v/BdSV71LrefKanXon6lvM6ls+4qw8+kesYRXKZshJV8wtJL bOr3hwP6+K//YJnJZVnfvbARRUTdciC8yKeHV7vrW7EbgVaMqkCx4IZfTyrFdgC3vM +3GZwOCoQWR9MN1GhUu0MT8VrzX5elV0PVHIR2Ow= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5A14B60588; Fri, 23 Mar 2018 06:11:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521785516; bh=zW8gwN2xBaQ+o40Oh619Mh7SE0QP+OAoyw9M4j7ZNZ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TD941cSHyM5z/YEJRARIk0uHA74B1joJF2aOXQ9bfQ6UGIn6O0Nnt98RslgZ0jQJj ImtHlGV2YxADjJsfMeBiLEH+seb9G1Vm60UgfqXJqyEmSnrh3GPBgHA+EA9BzUZ4e7 92//+egcUDpWjwjmQBU+UDW646uyIQf8CWsnWQKM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5A14B60588 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , linux-arm-msm@vger.kernel.org, Manu Gautam , stable , Vivek Gautam , Jaehoon Chung , Yoshihiro Shimoda Subject: [PATCH v3 2/6] phy: qcom-qusb2: Fix crash if nvmem cell not specified Date: Fri, 23 Mar 2018 11:41:23 +0530 Message-Id: <1521785487-29866-3-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521785487-29866-1-git-send-email-mgautam@codeaurora.org> References: <1521785487-29866-1-git-send-email-mgautam@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Driver currently crashes due to NULL pointer deference while updating PHY tune register if nvmem cell is NULL. Since, fused value for Tune1/2 register is optional, we'd rather bail out. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Reviewed-by: Vivek Gautam Cc: stable # 4.14+ Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 94afeac..40fdef8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -315,6 +315,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) const struct qusb2_phy_cfg *cfg = qphy->cfg; u8 *val; + /* efuse register is optional */ + if (!qphy->cell) + return; + /* * Read efuse register having TUNE2/1 parameter's high nibble. * If efuse register shows value as 0x0, or if we fail to find -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project