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[209.132.180.67]) by mx.google.com with ESMTP id bd3-v6si9792425plb.392.2018.03.23.11.23.01; Fri, 23 Mar 2018 11:23:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=lewZUrgD; dkim=pass header.i=@codeaurora.org header.s=default header.b=KB+r2Dgc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752284AbeCWSVs (ORCPT + 99 others); Fri, 23 Mar 2018 14:21:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41116 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751796AbeCWSVi (ORCPT ); Fri, 23 Mar 2018 14:21:38 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0B9A9607B9; Fri, 23 Mar 2018 18:21:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521829298; bh=qdaNCuGEfhsL2xTPZJN1aa73sO/AFcsHx2ZdmsYQFF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lewZUrgDLypFkHWtjn/IzHWXaIl6CpoIlCm4Czn033QnL32dUuK87IgNAaAy5giEY 1gvS5qs0sOL2Brecl+IJPHt+nyg2K4Rx7Izx8RyBLquSAItafVFp/ZNsgxpswHsRTZ drRcgT4m+nJGPtcEXsV+QvNBh+y03S5uXVeGzwJo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0B63E60FB1; Fri, 23 Mar 2018 18:21:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521829295; bh=qdaNCuGEfhsL2xTPZJN1aa73sO/AFcsHx2ZdmsYQFF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KB+r2Dgc8SimUuDIUiK7TcjJUSaDEzSywaXGCO/Lok8gSzMsmboNa0S+R9kCmgAjH yePhS1cKwbVLn0xrQb4JIc2tqfH5/MDeEXsAFFEGwhdf1REGR4t6k3ccsX9Wb9Io1q MclupMGDclSkh9fSyb+H6uSyjzdtBh3kLa+OFsHE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0B63E60FB1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Cc: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/7] ixgbevf: eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 14:21:17 -0400 Message-Id: <1521829277-9398-8-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> References: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Code includes wmb() followed by writel() in multiple places. writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c index 815cb1a..9e684b1 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c @@ -725,7 +725,12 @@ static void ixgbevf_alloc_rx_buffers(struct ixgbevf_ring *rx_ring, * such as IA-64). */ wmb(); - writel(i, rx_ring->tail); + writel_relaxed(i, rx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } } @@ -1232,7 +1237,12 @@ static int ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector, * know there are new descriptors to fetch. */ wmb(); - writel(xdp_ring->next_to_use, xdp_ring->tail); + writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } u64_stats_update_begin(&rx_ring->syncp); @@ -4004,7 +4014,12 @@ static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, tx_ring->next_to_use = i; /* notify HW of packet */ - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); return; dma_error: -- 2.7.4