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[209.132.180.67]) by mx.google.com with ESMTP id 126si714845pfw.399.2018.03.23.11.56.27; Fri, 23 Mar 2018 11:56:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=KXDFPtYp; dkim=pass header.i=@codeaurora.org header.s=default header.b=YrRrBiRV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752610AbeCWSzH (ORCPT + 99 others); Fri, 23 Mar 2018 14:55:07 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46250 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751541AbeCWSxJ (ORCPT ); Fri, 23 Mar 2018 14:53:09 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 87D4E601EA; Fri, 23 Mar 2018 18:53:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521831188; bh=kzU370DBYXzzwy/yY6S9SSuttXZgy6s8zEIJUcvya2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KXDFPtYp7IxE8dyAdpt1EG4gIHT3XbZmB3mIwsJLtxrGiEZwyQnYaldcGSNWTvQm4 xoi0QlT+rO26Oy5CYNvdvpgm9sw/RiOfhibovaL3uucUwCi6z2J1EDVwWpMxhtjLzH 39pOWlUL++qhJlnlKJKhFVp6UsQqmMnDWDmaU+7s= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A5A5760C66; Fri, 23 Mar 2018 18:53:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521831187; bh=kzU370DBYXzzwy/yY6S9SSuttXZgy6s8zEIJUcvya2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YrRrBiRVkKg7jXsMf/7yT6dlOmXxe4N9U4MXRX8l+JaB8qp3bYZ4RZWD7RGOESR4t Df6fl3/tpBqnQcHFXWthaLEB6meFi4PF3s8X3jewG5OQq1E+sX2zu0WMNEy8vZaS7x By3aVdLEAdJLa6Un4g4waqHCorHfzBTRRlDh6vZM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A5A5760C66 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Cc: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/7] ixgbe: eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 14:52:55 -0400 Message-Id: <1521831180-25014-3-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521831180-25014-1-git-send-email-okaya@codeaurora.org> References: <1521831180-25014-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Code includes wmb() followed by writel() in multiple places. writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index e3b32ea..fb80edb 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -1701,7 +1701,7 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) * such as IA-64). */ wmb(); - writel(i, rx_ring->tail); + writel_relaxed(i, rx_ring->tail); } } @@ -2470,7 +2470,7 @@ static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, * know there are new descriptors to fetch. */ wmb(); - writel(ring->next_to_use, ring->tail); + writel_relaxed(ring->next_to_use, ring->tail); xdp_do_flush_map(); } @@ -8101,7 +8101,7 @@ static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems @@ -10038,7 +10038,7 @@ static void ixgbe_xdp_flush(struct net_device *dev) * are new descriptors to fetch. */ wmb(); - writel(ring->next_to_use, ring->tail); + writel_relaxed(ring->next_to_use, ring->tail); return; } -- 2.7.4