Received: by 10.213.65.68 with SMTP id h4csp1125080imn; Mon, 26 Mar 2018 00:51:08 -0700 (PDT) X-Google-Smtp-Source: AG47ELtHNnqhMkndMQdn9FnMJwqmhrzz4YBpRHsYlpp3wU4HqrXIZ2gkhcc2+KTbkYwUPSA8uWU0 X-Received: by 2002:a17:902:d207:: with SMTP id t7-v6mr22825081ply.216.1522050668389; Mon, 26 Mar 2018 00:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522050668; cv=none; d=google.com; s=arc-20160816; b=0D6don8pYQchekGdTAd+IymHrh4VWp+mhxql3W3evz4guMTuyTbAVIYpy/HdABB3T+ BQLq3jtft/VdkDHUm2DM4N7NMDIqLlTzMuj8D2QiRFrGoDWf7U6R9bKAhpnYx46zNhFM a8F+nxKbBjYtcoy2oDHMu/84em3CjivbCK3vVTgPvmIcCtpC3HxJYoTuwh3rNPAgXSSs umY0scjuHwQJ9VzuyqeFIT2lpB7+SSwszxlqVHZEI4bfeSQKs4mL122BeeNnMAvC4C46 VOroAvSC8d+tqPfI8EYyBtoJGL8rs6srK2UCOUDSL95mA5M8yQzGv2tctsDs9w+InYyw U3oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject :dkim-signature:arc-authentication-results; bh=SDpySXBYqLYMTiFfzEVx5kClQiR4Kr25k33BaQja2i4=; b=Xt2Y16wB06hjCwTE1SCKW3Nvh/jOXHiNWFlDVRhxCnIdYlLYg1IuCuiJz0XOkJOg4Z WiUyZT1KVXD4deENMLxwwDUIAwl39ueWFxyM7UByouAhnFZA8Qk5SUzHhRrd8s5pIu8b GVqgqVThw1kSLrKIVxLJ6+hetvrS6By2DrRqKSqStyLoVPKzWVL0+FOkS7nj2rmOgy+7 PatmmuGzdqsnJKTjrz1rs5krTgcqixqwDHnztVer5OMKvBUSpHtJKePu0o5PKzGX1rx8 /zGpbbCgJ7cym5SwAEUi21wqJC6h9LD4/D9fYq9rB70Pmrre8KcBJIutINkEWlv7E1Sy W2CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=e3ex0d5P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j84si11138693pfj.177.2018.03.26.00.50.54; Mon, 26 Mar 2018 00:51:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=e3ex0d5P; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751489AbeCZHt4 (ORCPT + 99 others); Mon, 26 Mar 2018 03:49:56 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44947 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751141AbeCZHty (ORCPT ); Mon, 26 Mar 2018 03:49:54 -0400 Received: by mail-wr0-f193.google.com with SMTP id u46so17830563wrc.11 for ; Mon, 26 Mar 2018 00:49:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=SDpySXBYqLYMTiFfzEVx5kClQiR4Kr25k33BaQja2i4=; b=e3ex0d5PxN0xYiefnZyegffwmdwpHKNmvufXvceTKvgT2gFLMFOX9tJIDT4f1LfzzI CqTR8TVlipOWUb0ux7lmGx4tMF470mLK/H0ke8lIe4XVJjki8NjfsUH9gHsnJ7WszWqn NgIbffkhRI0FrRiHGyBPT/BrgQrvgPTWJBtz+2W5gXOSfj/P0Na7/R7dU6Ia30pKbu82 uwb3LRn71AeanEOoYoVHO+rK9OLf0Z8o3MvZyPbYYnILT5Ex/NrAlNAjad9nqIgMA8Y1 gw10zJl9lXSSNLO454Nmqwv4b21fdxvnqM5a/FPGRBI0bFlSWgU/6nisfiZsJ4QV7kyP +W2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=SDpySXBYqLYMTiFfzEVx5kClQiR4Kr25k33BaQja2i4=; b=SHc6GSRFYQey7QKlcyTggNch//YIwAlUUA/mNE68WoPYK+rgMVZ9FTW1nG1VZGRvRh IO5avPKFWkm2GRPHZ+BmPdTWSHGri3e6TiXSue3Ot2F2t3YDPWk669bNCNnYbomLJ+eH YBpvOotWi3LsKwRreVkJezuxk2UTmtpc25XPyf3Re+veo3MTTC0BkhF4at9QzeXArVx4 A3DTtXlF6PiyqDiYvC/ixch/cpIEuJhNNAS2RY+Q/CDq1nUPf0dj/VNzDcg/9DMgmVAf bjeiAR8IraqPxmdXN1RyJhRvJbUwZ3+NUuM7qg1kq3ITrpANEvX1Um7Zl33pghHAhZ+y uwIA== X-Gm-Message-State: AElRT7FBme/QXH+aTu2ABF92uk/cSWyexgLf2KuUDawNdAWQT0gnWq00 SYc+PMZwbNFWRQ8GtQF4os9PdQ== X-Received: by 10.223.191.11 with SMTP id p11mr29218143wrh.160.1522050592897; Mon, 26 Mar 2018 00:49:52 -0700 (PDT) Received: from [10.1.2.12] ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id k10sm10750932wmb.26.2018.03.26.00.49.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Mar 2018 00:49:52 -0700 (PDT) Subject: Re: [PATCH 1/4] dt-bindings: clock: meson: update documentation with hhi syscon To: Rob Herring , Jerome Brunet Cc: Kevin Hilman , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" References: <20180315115545.1884-1-jbrunet@baylibre.com> <20180315115545.1884-2-jbrunet@baylibre.com> <20180318125222.kqtybu4hiwvsx3om@rob-hp-laptop> <1521385797.6569.90.camel@baylibre.com> From: Neil Armstrong Organization: Baylibre Message-ID: <8712ae70-9771-4438-68e2-9e4b37332de8@baylibre.com> Date: Mon, 26 Mar 2018 09:49:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/03/2018 04:04, Rob Herring wrote: > On Sun, Mar 18, 2018 at 10:09 AM, Jerome Brunet wrote: >> On Sun, 2018-03-18 at 07:52 -0500, Rob Herring wrote: >>> On Thu, Mar 15, 2018 at 12:55:42PM +0100, Jerome Brunet wrote: >>>> The HHI register region hosts more than just clocks and needs to >>>> accessed drivers other than the clock controller, such as the display >>>> driver. >>>> >>>> This register region should be managed by syscon. It is already the case >>>> on gxbb/gxl and it soon will be on axg. The clock controllers must use >>>> this system controller instead of directly mapping the registers. >>> >>> Sounds like a kernel problem, not a DT one. >> >> It's a platform problem, so it has much a kernel problem (solution already >> merged) as a DT problem >> >> DT wise, we've got two devices mapping the same region >> >> in arch/arm64/boot/dts/amlogic/meson-gx.dtsi: >>> system-controller@0 >> >> which is used by the display device. >> >> and in arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi (same for gxl) >>> clock-controller@0 >> >> It has worked so far because the clock controller claims the region w/o >> reserving it but it remains unsafe since both device may access the same region. >> The fix is to have the clock controller go through the existing syscon. > > We certainly want to avoid multiple nodes using the same mmio region. > > >>> With a single child, there is really no point to this change. A single >>> node can provide multiple functions. Look at nodes that are both reset >>> and clock providers. >> >> There is more than a single user, as explained above and in the cover letter of >> this series. > > Right, but a single node can support more than a single user (or > provider). You don't have to have multiple nodes to have multiple > users/providers. > > Rob > Hi Rob, It's a question about user/provider, the syscon node represents the entire mmio region which has multiple sparse registers for multiple features, is used indirectly by the display driver, ... and has multiple features, non limited to, clock controller, multiple power domains,... and it is simpler to represent these as subnodes instead of a big fat node. Today, it is already represented like this within the Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt So this binding is only an extension for the clock controller which was mis-architectured at the time due to a mis-knowledge of the HW architecture. Neil