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[209.132.180.67]) by mx.google.com with ESMTP id u11-v6si14202222pls.735.2018.03.26.02.14.13; Mon, 26 Mar 2018 02:14:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kHXvrECs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751937AbeCZJMa (ORCPT + 99 others); Mon, 26 Mar 2018 05:12:30 -0400 Received: from mail-it0-f65.google.com ([209.85.214.65]:51830 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751083AbeCZJMG (ORCPT ); Mon, 26 Mar 2018 05:12:06 -0400 Received: by mail-it0-f65.google.com with SMTP id j137-v6so9792142ita.1 for ; Mon, 26 Mar 2018 02:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=wTN6VK6DZjNtTRTYBL37mUkIRJ598WYs0pzCfgva2i8=; b=kHXvrECstOB1oucOsgLcwNyEc8M+qv/NpgKk8iSUuOCrDM8YcsG8b1QhKpZXe2doo4 a1Oeq8OecwRQ8wnlmh2ZT+n/bYbqHYXcEYjYuzevtmdQXW7qAiU8ZZnZcL2WQrJhTYYk BhO99lt/qW0rCrk4W6hjQPmWqyPLZWsjxEGDg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=wTN6VK6DZjNtTRTYBL37mUkIRJ598WYs0pzCfgva2i8=; b=PgUr+BUwmoBqlY8HZrRfL+42hbsQ6GlYkaYgQgbkvS6mi+bkPqrYhHcxb0fdfNEfR2 49r19OSKFTV6kJYGxdDzXiwE3CFbZ1AYdc1tuRUUl3HLN8ub/rl4m6m9Nh+YXcXov412 AdVTwNX33HymrBCvnCAbPAWcGuWAgvf8Dh5sjXoPWpd2dWMfZA4KCA1u2nGlHlz3Hyh2 NWRhK5ce4ySq131r/QQgMMpqMpxVHo+tYAlSipry4zyBRfHjJVWgI9Fmq+wVPvvHS/en nT426b6KT3UyLt/CIUFEYjFXt0LG42nHOv4PGcKK+u9HgmaU8UsqEC1c+L9LSFs34O3g kxrA== X-Gm-Message-State: AElRT7HVZnDhNpzZtFZR+C0JTYV7cF6OK27EQ+p2Ps7sTaDWMGlnkgAN NQFwrfRprhTJqto/03psIanFVWRJLryInuIXIl/d7A== X-Received: by 2002:a24:730e:: with SMTP id y14-v6mr21701054itb.70.1522055525440; Mon, 26 Mar 2018 02:12:05 -0700 (PDT) MIME-Version: 1.0 Received: by 10.79.207.141 with HTTP; Mon, 26 Mar 2018 02:12:04 -0700 (PDT) In-Reply-To: <20180312164530.215524-1-djkurtz@chromium.org> References: <20180312164530.215524-1-djkurtz@chromium.org> From: Linus Walleij Date: Mon, 26 Mar 2018 11:12:04 +0200 Message-ID: Subject: Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq To: Daniel Kurtz , Shyam Sundar S K , Nehal Shah , Ken Xue Cc: adurbin@chromium.org, "open list:PIN CONTROL SUBSYSTEM" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 12, 2018 at 5:45 PM, Daniel Kurtz wrote: > In certain cases interrupt enablement will be delayed relative to when > the InterruptEnable bits are written. One example of this is when > a GPIO's "debounce" logice is first enabled. After enabling debounce, > there is a 900 us "warm up" period during which InterruptEnable[0] > (bit 11) will read as 0 despite being written 1. During this time > InterruptSts will not be updated, nor will interrupts be delivered, even > if the GPIO's interrupt configuration has been written to the register. > > To work around this delay, poll the InterruptEnable bits after setting > them to ensure interrupts have truly been enabled in hardware before > returning from the irq_enable handler. > > Signed-off-by: Daniel Kurtz Patch applied. I see the AMD people were not on CC so adding them here so they can say if there is any problem with the approach. Daniel: maybe you should consider listing yourself as comaintainer of this driver? Yours, Linus Walleij