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[209.132.180.67]) by mx.google.com with ESMTP id 4-v6si15136677plc.59.2018.03.26.07.41.26; Mon, 26 Mar 2018 07:41:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Qt1dAweN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752173AbeCZOkZ (ORCPT + 99 others); Mon, 26 Mar 2018 10:40:25 -0400 Received: from mail-qk0-f175.google.com ([209.85.220.175]:45901 "EHLO mail-qk0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751866AbeCZOkX (ORCPT ); Mon, 26 Mar 2018 10:40:23 -0400 Received: by mail-qk0-f175.google.com with SMTP id s9so20303814qke.12; Mon, 26 Mar 2018 07:40:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=PWpaAq8WTSxTslzNVFc5uhwqSJj37620hCEkRtEdv58=; b=Qt1dAweNnTrFRK7vYqhymM2KwifA830jfG5tncIFoMDAuvGZCatppGprDCvwuYPKUY d/lD4oGEOBzGrm86WNfKOWnoAC1Dd+5xzxnh6RSblztJxQnrFQnk19Z0MpJ12PA+mXwL 2NAHslRrDlfR/AARBqxzjLs6ghDni399WTPgeI31jFPCbrUfyZIcwMUJ7gOdhihFK+1I uJ8I/pD0VDqzMIxrMDN7XJ6/oM0YnJg68369RK93KrsacXIeCjZ0nD/t+rTYP2wb3nRn wunX9rLJofPoJKhsbGb813fA/hrQWyqcRX2ZIK4dQAiw41QfDGmKMQ9K+kTGvSKFPX+v rQrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=PWpaAq8WTSxTslzNVFc5uhwqSJj37620hCEkRtEdv58=; b=lsJ4e4nMkYybx890bFqZt4yrkLtFT/Ps5IqKNlyZCrROCHLfGoOv5ZJ2s0+D4/iCMT fUdIp7lTmp/z1GWXZqtzgHVOlws1kHPBn92gvoxEkyJzEwIRP+dbmFG/4mPwvNZPlj87 UBojztIeaMpdZKfMWvc52HG6XkblDKeT1Ra2eTdZKRe32nJb/6ccLLCgdJEGtZLkUDPX /WRdsWX4l9xslJp12mpXNX5+3JqMAezW3+9hvyykT3xD06ae0myFam4er3c1QSX+gNzb uw1r02xCH3Fj9ZJNRk64WvV10OnIDg4+x5DBBZD5X590HE1vJNHvEUoDmA46KyShRaTV N+Og== X-Gm-Message-State: AElRT7Ep/febrVbasJcD+oz2q5JN3qN7k8S3yt0hUQNtQ3iz5xEU6Z6w ReOed0fhamvheMBFtnAhewah3ddX4YLC6shEY90= X-Received: by 10.55.159.201 with SMTP id i192mr54861469qke.125.1522075222014; Mon, 26 Mar 2018 07:40:22 -0700 (PDT) MIME-Version: 1.0 Received: by 10.200.17.138 with HTTP; Mon, 26 Mar 2018 07:40:21 -0700 (PDT) In-Reply-To: <20180326104205.GA12425@amd> References: <20180326095213.18362-1-enric.balletbo@collabora.com> <20180326104205.GA12425@amd> From: Enric Balletbo Serra Date: Mon, 26 Mar 2018 16:40:21 +0200 Message-ID: Subject: Re: [PATCH v6 1/5] pwm-backlight: enable/disable the PWM before/after LCD enable toggle. To: Pavel Machek Cc: Enric Balletbo i Serra , Lee Jones , Daniel Thompson , Jingoo Han , Rob Herring , Heiko Stuebner , Thierry Reding , Bartlomiej Zolnierkiewicz , Richard Purdie , Jacek Anaszewski , Linux PWM List , linux-fbdev@vger.kernel.org, linux-kernel , Guenter Roeck , "open list:ARM/Rockchip SoC..." , linux-leds@vger.kernel.org, "devicetree@vger.kernel.org" , kernel@collabora.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Pavel, 2018-03-26 12:42 GMT+02:00 Pavel Machek : > On Mon 2018-03-26 11:52:09, Enric Balletbo i Serra wrote: >> Before this patch the enable signal was set before the PWM signal and >> vice-versa on power off. This sequence is wrong, at least, it is on >> the different panels datasheets that I checked, so I inverted the sequence >> to follow the specs. >> >> For reference the following panels have the mentioned sequence: >> - N133HSE-EA1 (Innolux) >> - N116BGE (Innolux) >> - N156BGE-L21 (Innolux) >> - B101EAN0 (Auo) >> - B101AW03 (Auo) >> - LTN101NT05 (Samsung) >> - CLAA101WA01A (Chunghwa) > > Ok, but this changes behaviour for other panels, too. Are you sure you > are not breaking one of those? I can't say that I am 100% sure because I didn't find all the datasheets of all the panels supported in the kernel. But all the datasheets I checked specifies this sequence as valid. In general I think that doesn't really matter, but I know that at least the B116XTN02 panel requires enable first the PWM, wait 10ms and then enable BL_EN to avoid garbage. So the other way around is not valid for this panel. That's the reason for this patchset. If anyone knows a panel that says the contrary, please let me know and I'll try to rework the patches to satisfy both requirements. Regards, Enric > Pavel > > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html