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[209.132.180.67]) by mx.google.com with ESMTP id z21-v6si1537509plo.225.2018.03.27.09.20.31; Tue, 27 Mar 2018 09:20:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=S4fLQ/Nl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751765AbeC0QT1 (ORCPT + 99 others); Tue, 27 Mar 2018 12:19:27 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:38672 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750937AbeC0QT0 (ORCPT ); Tue, 27 Mar 2018 12:19:26 -0400 Received: by mail-pl0-f68.google.com with SMTP id m22-v6so14403816pls.5 for ; Tue, 27 Mar 2018 09:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:cc:from:to; bh=o4eIISOLsPi2KSg16GZP3XtCtB/wAP2e6/dO/bjLsf0=; b=S4fLQ/NlIO5kjlZvfXdA2SA44nDxQRHsV0qVU0ZctFd4RQ7WzE3sNugJxxpl4X6EyN FeuOuVuKxK/zxWKFPXY0CtPPnb+XEmrpv+3fquFd5jPE3l9/z62Ou63TBCWL4SruBBlR MRq94Fo62klUk2CPsWbX7YDj9Xvp/1zec/iFri9K0rAb/bspJ01YiwLT+y6xelydfzMi WfMPvmyN0qZMAz8vBdjgj8y5xPJABk9MYVV4rxh5uc8F4L+Q8wFOpkjrdVqPJGSY19Fk Ap+iYa0BUWB7YFTKy3lGZFyfRUN0dQfmYbMFr2BidrgKg/x6n0E+yRUaWo3iGCecaEdb ugJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=o4eIISOLsPi2KSg16GZP3XtCtB/wAP2e6/dO/bjLsf0=; b=pNdGOi0/wWgDQ1BNSUy/f+nXczNwLKLAtVXEmZS9+KqJEMkROsDvsehHslJ828gX74 T8UDAX8jpJyowBix0guuVOW2LFfXdIR4T8hSuR6ofG83K0Bkh//shtZTivfG8S0JgA6Q CnKJyXtPQInNX7rQ8aICOj0HELOUwt5IbQMhyWnmi6hjg7bjHpiSp2sHO2mmXUyoIHbI zRwzZzTxgamih8VHc1CXRTstudmwjmKc2aBzO4v1D0yZ8Y9EmJee1ndy9oS1erXMLxQS ritDTNnY13rPQ8JWVX42kTZ1HVn1EisXi17BAMoUpLfqFHKoGqEepEMnaZ9y+rehfTpc /okw== X-Gm-Message-State: AElRT7F8cC2PKOzvmkM8yA6e7BMfnvxigqV0KQR0Y4CTKMdLK2OTUnOT 2uaVnjj+iYxQSgoTxID+tSUCfg== X-Received: by 2002:a17:902:2862:: with SMTP id e89-v6mr45430317plb.348.1522167565856; Tue, 27 Mar 2018 09:19:25 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id z14sm3114133pgv.26.2018.03.27.09.19.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Mar 2018 09:19:25 -0700 (PDT) Subject: Make set_handle_irq and handle_arch_irq generic, v4 Date: Tue, 27 Mar 2018 09:19:03 -0700 Message-Id: <20180327161911.14086-1-palmer@sifive.com> X-Mailer: git-send-email 2.16.1 Cc: Arnd Bergmann From: Palmer Dabbelt To: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is my third version of this patch set, but the original cover letter is still the most relevant description I can come up with. This patch set has been sitting around for a while, but it got a bit lost in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for interrupt handling) to our first-level interrupt controller. While this isn't completely crazy (as the first-level interrupt controller is specified by the ISA), it is a bit awkward. This patch set decouples our trap handler from our first-level IRQ chip driver by copying what a handful of other architectures are doing. This does add an additional load to the interrupt handling path, but there's a handful of performance problems in there that I've been meaning to look at so I don't mind adding another one for now. The advantage is that our irqchip driver is decoupled from our arch port, at least at compile time. Hopefully this time I've managed to produce a properly bisectable patch set. There were two big bugs in the last version: * I missed the generic irqchip drivers that set MULTI_IRQ_HANDLER. This caused all sorts of non-defconfig ARM builds to fail. * MULTI_IRQ_HANDLER and GENERIC_IRQ_MULTI_HANDLER could both get set by randconfig builds. This caused the patch set to be non-bisectable. I've gone through a bit of a song-and-dance to work around these, but I think it's sound. The patch set works as follows (the order is important): * MULTI_IRQ_HANDLER is added to the arm64 and openriscv ports, forced to true. Nothing in these ports actually looks at CONFIG_MULTI_IRQ_HANDLER (it's forced to true anyway, so there's no point in looking), it's just there to indicate that set_handle_irq() is defined by these ports. * Every generic irqchip driver is modified to set GENERIC_IRQ_MULTI_HANDLER, but only if MULTI_IRQ_HANDLER is false. These generic drivers depend on set_handle_irq() so they need one of these symbols to be set, but the two Kconfig symbols are mutually exclusive so I can't just select both (I just found out that select ignores dependencies :)). * GENERIC_IRQ_MULTI_HANDLER is added to all ports, with a dependency on !MULTI_IRQ_HANDLER as they define the same symbols. * Support for GENERIC_IRQ_MULTI_HANDLER is added to the RISC-V, arm, arm64, and openrisc ports. This is a pretty mechanical change for the other ports (just changing the #ifdefs), and a simple one for the RISC-V port. This patch set assumes that the two patches currently on tip are dropped, but if that's not OK then I can create another patch set based on those two. Of course, it won't be fully bisectable (arm randconfig will still be broken somewhere in the middle). I built this patch set after patches 3, 7, and 8 on arm, arm64, and openrisc defconfigs as well as an arm randconfig that broke my v3 patch set. Sorry for breaking things, hopefully it works this time! Changes since v3: * There's now three new patches: #1 and #2 add MULTI_IRQ_HANDLER on arm64 and openrisc so they match ARM, while #8 removes all MULTI_IRQ_HANDLER references. * All the generic irqchip drivers have been converted from MULTI_IRQ_HANDLER to GENERIC_IRQ_MULTI_HANDLER. * A handful of commit messages have been cleaned up. Changes since v2: * This is now called CONFIG_GENERIC_IRQ_MULTI_HANDLER instead of MULTI_IRQ_HANDLER. * Rather than converting the ARM code to generic code, this adds new generic code (based on the ARM implementation) and then provides separate patches to convert each architecture over to use CONFIG_GENERIC_IRQ_MULTI_HANDLER. Changes since v1: * I based this on arm instead of arm64, which means we guard the selection of these routines with CONFIG_MULTI_IRQ_HANDLER. * The changes are in kernel/irq/handle.c and include/linux/irq.h instead of lib. * I've converted the arm, arm64, and openrisc ports to use the generic versions of these routines. [PATCH v4 1/8] arm64: Set CONFIG_MULTI_IRQ_HANDLER [PATCH v4 2/8] openrisc: Set CONFIG_MULTI_IRQ_HANDLER [PATCH v4 3/8] irq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER [PATCH v4 4/8] RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER [PATCH v4 5/8] arm: Convert to GENERIC_IRQ_MULTI_HANDLER [PATCH v4 6/8] arm64: Use the new GENERIC_IRQ_MULTI_HANDLER [PATCH v4 7/8] openrisc: Use the new GENERIC_IRQ_MULTI_HANDLER [PATCH v4 8/8] irq: Remove MULTI_IRQ_HANDLER as it's now obselete