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[209.132.180.67]) by mx.google.com with ESMTP id p3si1894369pfh.84.2018.03.27.18.57.10; Tue, 27 Mar 2018 18:57:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=ZKZxA5Yq; dkim=pass header.i=@codeaurora.org header.s=default header.b=nqSExfel; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752706AbeC1Bzi (ORCPT + 99 others); Tue, 27 Mar 2018 21:55:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60560 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752394AbeC1Bzh (ORCPT ); Tue, 27 Mar 2018 21:55:37 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4348A607B9; Wed, 28 Mar 2018 01:55:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522202137; bh=FXF7dMB24cXsedTlTW8t/b2khKzIi9pzG1la493PP7w=; h=From:To:Cc:Subject:Date:From; b=ZKZxA5YqwV/KNOG7zbi58136AhJs/Ma4EQbBTaKok3FmOCovtSWdbvvSI3SyK5pnF VKIbVvuAsh5ZnBelBonVeiY0yv+PuJyiz2tlcMknC+TU8lC+3gZE0jiPCNgjJAEioW T8ZebK8I1obLlxo98tb/oEld2PjW+yF7egPDI4Jo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from krakatau.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pelcan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id ED7BA601EA; Wed, 28 Mar 2018 01:55:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522202136; bh=FXF7dMB24cXsedTlTW8t/b2khKzIi9pzG1la493PP7w=; h=From:To:Cc:Subject:Date:From; b=nqSExfelekrc0N4jS5nPR7Paukn8xWVsyRAXo5vCpB3gDg16Wj5gTpK+b9Zheyrn3 QkWOmB1LFqGPyFt0548sz5UbNBrzvgbEGhtqauuNWbgYMRcGxMzpLUoUJ+2Q4OkF8W 7Bg/pJ3saDLIfGREY+zoNGVcYpGt277jyC4lNIg0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org ED7BA601EA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=pelcan@codeaurora.org From: Philip Elcan To: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland , Robin Murphy , linux-kernel@vger.kernel.org Cc: Thomas Speier , Shanker Donthineni Subject: [PATCH V3] arm64: tlbflush: avoid writing RES0 bits Date: Tue, 27 Mar 2018 21:55:32 -0400 Message-Id: <1522202132-16998-1-git-send-email-pelcan@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Several of the bits of the TLBI register operand are RES0 per the ARM ARM, so TLBI operations should avoid writing non-zero values to these bits. This patch adds a macro __TLBI_VADDR(addr, asid) that creates the operand register in the correct format and honors the RES0 bits. Signed-off-by: Philip Elcan --- arch/arm64/include/asm/tlbflush.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..dfc61d7 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -60,6 +60,15 @@ __tlbi(op, (arg) | USER_ASID_FLAG); \ } while (0) +/* This macro creates a properly formatted VA operand for the TLBI */ +#define __TLBI_VADDR(addr, asid) \ + ({ \ + unsigned long __ta = (addr) >> 12; \ + __ta &= GENMASK_ULL(43, 0); \ + __ta |= (unsigned long)(asid) << 48; \ + __ta; \ + }) + /* * TLB Management * ============== @@ -117,7 +126,7 @@ static inline void flush_tlb_all(void) static inline void flush_tlb_mm(struct mm_struct *mm) { - unsigned long asid = ASID(mm) << 48; + unsigned long asid = __TLBI_VADDR(0, ASID(mm)); dsb(ishst); __tlbi(aside1is, asid); @@ -128,7 +137,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { - unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); + unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); __tlbi(vale1is, addr); @@ -146,7 +155,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end, bool last_level) { - unsigned long asid = ASID(vma->vm_mm) << 48; + unsigned long asid = ASID(vma->vm_mm); unsigned long addr; if ((end - start) > MAX_TLB_RANGE) { @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, return; } - start = asid | (start >> 12); - end = asid | (end >> 12); + start = __TLBI_VADDR(start, asid); + end = __TLBI_VADDR(end, asid); dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { @@ -185,8 +194,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end return; } - start >>= 12; - end >>= 12; + start = __TLBI_VADDR(start, 0); + end = __TLBI_VADDR(end, 0); dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) @@ -202,7 +211,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end static inline void __flush_tlb_pgtable(struct mm_struct *mm, unsigned long uaddr) { - unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); + unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm)); __tlbi(vae1is, addr); __tlbi_user(vae1is, addr); -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.