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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=UDMUUT4o9C83gOOEy/IK2/OX35SJkNmnhgSnOk2WExE=; b=ErCHHLOpn312UHy8GtaA7Q4b1LYSNobqx0uDQ7A9J4OF6GhwKhNAyFo1JtS0Gv3LJIwqDd6qoEsdUsCnW9N18p3C2MDB7vz23hFTxHjsAhCplLxjRYqxzXv/wlAA6bl1c9JpUd+iGl2bV+wAan4hq6c6FkfXCvOjnoZE5znFoGg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Nehal-bakulchandra.Shah@amd.com; Received: from [10.136.6.59] (202.56.249.162) by MW2PR12MB2571.namprd12.prod.outlook.com (2603:10b6:907:a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.609.10; Wed, 28 Mar 2018 05:20:14 +0000 Subject: Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq To: Linus Walleij , Daniel Kurtz , Shyam Sundar S K , Ken Xue References: <20180312164530.215524-1-djkurtz@chromium.org> Cc: adurbin@chromium.org, "open list:PIN CONTROL SUBSYSTEM" , open list From: "Shah, Nehal-bakulchandra" Message-ID: Date: Wed, 28 Mar 2018 10:49:49 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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One example of this is when >> a GPIO's "debounce" logice is first enabled. After enabling debounce, >> there is a 900 us "warm up" period during which InterruptEnable[0] >> (bit 11) will read as 0 despite being written 1. During this time >> InterruptSts will not be updated, nor will interrupts be delivered, even >> if the GPIO's interrupt configuration has been written to the register. >> >> To work around this delay, poll the InterruptEnable bits after setting >> them to ensure interrupts have truly been enabled in hardware before >> returning from the irq_enable handler. >> >> Signed-off-by: Daniel Kurtz > > Patch applied. > > I see the AMD people were not on CC so adding them here so they can > say if there is any problem with the approach. > > Daniel: maybe you should consider listing yourself as comaintainer of this > driver? > > Yours, > Linus Walleij > Looks good. Regards Nehal Shah