Received: by 10.213.65.68 with SMTP id h4csp106143imn; Tue, 27 Mar 2018 23:13:24 -0700 (PDT) X-Google-Smtp-Source: AIpwx480zH0wvCB8dofpfI+Idz+L0yhRuYHNVaKTuDI7mTxm9pxjEey7IT33tZwiYdoSiK8TQ0b1 X-Received: by 10.99.101.193 with SMTP id z184mr1642109pgb.429.1522217604095; Tue, 27 Mar 2018 23:13:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522217604; cv=none; d=google.com; s=arc-20160816; b=J3RpCg+P4OoF5Bh8+L0NDYib9Sbu18e0D+GXgVKziizdZj3SQuKtmSv2WEA6zxryHz sjK3qsIOvkKvmWCFrDzmysBdxT1AySw4QSidAMsL7kVtOOxPEXTFrlLLXMsMmdhRaw87 pNq9hWumwcTuLQn43k27MVaoIaTu89zGnN29KdQxANfSh9jOsWgGCVaXX8V8gjxl0NLv NOQP5efVlrVXSFEOuB8ALRDS7lhdVOZkZFCtAb9l+cZB1fOHk/YZ6rpgVPMdbOujBHwS yU5bQAgrmh0Yuls+S20u6XTYtevG7yeIqnoaL/PkM46KDvlVAbqILzWCmG2t+fQVlvgh 58KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:in-reply-to :mime-version:user-agent:date:message-id:from:cc:references:to :subject:arc-authentication-results; bh=GYAgU7Kvn+99Y6HssolgdKzhMxWKWXVhx05wplTeGSc=; b=mPTDuOx3Y3IiRQmScFXK0UqU6HOj9reQvfESNHe1QXL8WBUWZwmcAexVqW3u6nwVEQ 6BpF9W58VPQXbvTFPql+6KfmpSab3msB7YmPYPcu3KBngJTEBQ8rAzHHhSLE+6XSYPcB xp5fKqR4feYn+69q5ahCiyDq/IHGU1asj+k2ITm1cV8vycv33WTMtH3jI1oau45A64ja MH0rJ+O/YQ9FeOYdAbZ30rcFGW9MC1v4BfBulIuYVZ/lkG4Lk4C3dYoo6fSFhpljt82W OURWbv3rWOhOWjAFN458zXajJkQyVm6RpxynkxccalGaSpMhhRzXw3lyQElWQWh9U9Zs PgKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l5-v6si3338345pls.144.2018.03.27.23.13.08; Tue, 27 Mar 2018 23:13:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752159AbeC1GME (ORCPT + 99 others); Wed, 28 Mar 2018 02:12:04 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6697 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751908AbeC1GMC (ORCPT ); Wed, 28 Mar 2018 02:12:02 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9EFA945AD02EB; Wed, 28 Mar 2018 14:11:45 +0800 (CST) Received: from [127.0.0.1] (10.177.29.40) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.361.1; Wed, 28 Mar 2018 14:11:38 +0800 Subject: Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant To: Vivek Gautam References: <20180313085534.11650-1-vivek.gautam@codeaurora.org> <20180313085534.11650-6-vivek.gautam@codeaurora.org> <61d30fff-1bf8-d2c1-bbe9-f93de836ae77@huawei.com> <7d5af071-ef98-8461-3ce9-e84fc0b3956a@codeaurora.org> CC: , , , , , , , Will Deacon , Gaojianbo From: Yisheng Xie Message-ID: Date: Wed, 28 Mar 2018 14:11:07 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <7d5af071-ef98-8461-3ce9-e84fc0b3956a@codeaurora.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.29.40] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Vivek, On 2018/3/28 12:37, Vivek Gautam wrote: > Hi Yisheng > > > On 3/28/2018 6:54 AM, Yisheng Xie wrote: >> Hi Vivek, >> >> On 2018/3/13 16:55, Vivek Gautam wrote: >>> +- power-domains: Specifiers for power domains required to be powered on for >>> + the SMMU to operate, as per generic power domain bindings. >>> + >> In this patchset, power-domains is not used right? And you just do the clock gating, >> but not power gating, right? > > We are handling the power-domains too. Please see the example in this binding doc. I see, but I do not find the point in code of these patchset, do you mean PMIC(e.g mmcc) will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC suspend? > >> >> Another question is if smmu do power gating, it will reset some of its registers, so >> it need save at suspend and restore at resume, right? > > Qualcomm implementation of the arm-smmu has the retenetion enabled. So the smmu doesn't > loose state when power is pulled out of it. > And now we are just selectively enabling the runtime pm. So only the platforms that can really > support runtime pm can enable it. Get it, thanks for your explain. Thanks Yisheng > > Thanks > Vivek >> >> Thanks >> Yisheng >> > > >