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Date:   Wed, 28 Mar 2018 12:58:04 +0100
From:   Will Deacon <will.deacon@arm.com>
To:     Shanker Donthineni <shankerd@codeaurora.org>
Cc:     Mark Rutland <mark.rutland@arm.com>,
        Philip Elcan <pelcan@codeaurora.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        linux-kernel@vger.kernel.org,
        Thomas Speier <tspeier@codeaurora.org>,
        Robin Murphy <robin.murphy@arm.com>,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2] arm64: tlbflush: avoid writing RES0 bits
Message-ID: <20180328115804.GD30850@arm.com>
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On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> >>>> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
> >>>> ????????? return;
> >>>> ????? }
> >>>> ? -??? start = asid | (start >> 12);
> >>>> -??? end = asid | (end >> 12);
> >>>> +??? start = __TLBI_VADDR(start, asid);
> >>>> +??? end = __TLBI_VADDR(end, asid);
> > 
> > Can you test this bit too, please? ;)
> > 
> 
> I've verified the basic boot functionality on QDF2400 platform. But I can see now
> after your comments, it leads to TLB conflicts because of ASID is truncated to zero
> due to two times 48bit shift.     
> 
> Thanks for catching this one.

I just noticed it during review. In general, if you're making changes
relating to virtual memory stuff I'd *strongly* advise you to do more
than a basic boot test. It's amazing how much appears to run fine when
stuff like TLB invalidation is completely broken.

Anyway, thanks for turning around a new version so quickly.

Will