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[209.132.180.67]) by mx.google.com with ESMTP id q1-v6si3492431plr.182.2018.03.28.05.32.45; Wed, 28 Mar 2018 05:33:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=LwWET+VB; dkim=pass header.i=@codeaurora.org header.s=default header.b=HwbnZ8PZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752694AbeC1Mbl (ORCPT + 99 others); Wed, 28 Mar 2018 08:31:41 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58408 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752705AbeC1Mbi (ORCPT ); Wed, 28 Mar 2018 08:31:38 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 755DE60C65; Wed, 28 Mar 2018 12:31:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522240298; bh=YbKpeaDfaxVxHh0N6GmXOyLYZ5vFS6fs/Mheflig0xc=; h=From:To:Cc:Subject:Date:From; b=LwWET+VBLDzHhxhY7R0OWdA/H25DIQCHmthu53DBvtF/S1tCitA3oerOXf6y94bmJ JS3Z35DAhT30r4ewW8P/xy/YUuJ2Bua4JjljrricZtsCO3YXIuaxHp9B9k42mtaJey MxqHtvB5znKwjYkSJxatXP0FClJEe3PDptrUCTYU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from cpandya-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cpandya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 14FF960591; Wed, 28 Mar 2018 12:31:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522240297; bh=YbKpeaDfaxVxHh0N6GmXOyLYZ5vFS6fs/Mheflig0xc=; h=From:To:Cc:Subject:Date:From; b=HwbnZ8PZ0jO4tcKZahzx479xAHwLwg8pYpgFiStAjeglyIhT4e7iW96wfz8jvJvmb nEC1CIiOtm2miGXwHT8jNnoTDcDHGs7rPYuP8WzE3plivOrN8y2RqPWwT2rONXwdNZ nANOfCQu3EX64XFON+dsI1NXkOkCukboDLUK7uxE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 14FF960591 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cpandya@codeaurora.org From: Chintan Pandya To: catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, toshi.kani@hpe.com Cc: arnd@arndb.de, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, james.morse@arm.com, kristina.martsenko@arm.com, takahiro.akashi@linaro.org, gregkh@linuxfoundation.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, akpm@linux-foundation.org, Chintan Pandya Subject: [PATCH v7 0/4] Fix issues with huge mapping in ioremap for ARM64 Date: Wed, 28 Mar 2018 18:01:18 +0530 Message-Id: <1522240282-12104-1-git-send-email-cpandya@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series of patches are follow up work (and depends on) Toshi Kani 's patches "fix memory leak/ panic in ioremap huge pages". This series of patches are tested on 4.9 kernel with Cortex-A75 based SoC. These patches can also go into '-stable' branch (if accepted) for 4.6 onwards. From V6->V7: - Fixed compilation issue in x86 case - V6 patches were not properly enumarated From V5->V6: - Use __flush_tlb_kernel_pgtable() for both PUD and PMD. Remove "bool tlb_inv" based variance as it is not need now - Re-naming for consistency From V4->V5: - Add new API __flush_tlb_kernel_pgtable(unsigned long addr) for kernel addresses From V3->V4: - Add header for 'addr' in x86 implementation - Re-order pmd/pud clear and table free - Avoid redundant TLB invalidatation in one perticular case From V2->V3: - Use the exisiting page table free interface to do arm64 specific things From V1->V2: - Rebased my patches on top of "[PATCH v2 1/2] mm/vmalloc: Add interfaces to free unmapped page table" - Honored BBM for ARM64 Chintan Pandya (4): ioremap: Update pgtable free interfaces with addr arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable arm64: Implement page table free interfaces Revert "arm64: Enforce BBM for huge IO/VMAP mappings" arch/arm64/include/asm/tlbflush.h | 6 ++++++ arch/arm64/mm/mmu.c | 37 +++++++++++++++++++++++++------------ arch/x86/mm/pgtable.c | 8 +++++--- include/asm-generic/pgtable.h | 8 ++++---- lib/ioremap.c | 4 ++-- 5 files changed, 42 insertions(+), 21 deletions(-) -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project