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([2001:41d0:fe90:b800:b0a9:da92:8c72:d9e2]) by smtp.googlemail.com with ESMTPSA id k8sm2411101edn.37.2018.03.28.07.36.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Mar 2018 07:36:36 -0700 (PDT) Subject: Re: [PATCH v3 0/6] clocksource: rework Atmel TCB timer driver To: Alexandre Belloni Cc: Alexander Dahl , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Boris Brezillon , Thomas Gleixner References: <20180223171558.7037-1-alexandre.belloni@bootlin.com> <9761072.pX2B0LJlSJ@ada> <989df8a3-462a-c645-87f1-9f956e1b22c9@linaro.org> <4073350.0MmxRoANOi@ada> <6d43177a-bbea-6a01-5fa5-1c7891e18412@linaro.org> <20180328141645.GF13942@piout.net> From: Daniel Lezcano Message-ID: <75e5917b-a9ba-c67e-e964-3f002681f9bb@linaro.org> Date: Wed, 28 Mar 2018 16:36:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180328141645.GF13942@piout.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/03/2018 16:16, Alexandre Belloni wrote: > On 28/03/2018 at 15:03:11 +0200, Daniel Lezcano wrote: >> On 28/03/2018 12:29, Alexander Dahl wrote: >>> Hello Daniel, >>> >>> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano: >>>> Can you can give a rough amount for the irq rate on the timer ? >>> >>> I used itop [1] now to get a rough estimate. First with kernel v4.14.29-rt25 >>> (fully preempt RT): >>> >>> INT NAME RATE MAX >>> 19 [ vel tc_clkevt] 397 Ints/s (max: 432) >>> 26 [ vel eth0] 4 Ints/s (max: 38) >>> >>> Next test with kernel v4.15.13 gives (slightly slower, but non-RT): >>> >>> INT NAME RATE MAX >>> 19 [ vel tc_clkevt] 248 Ints/s (max: 273) >>> 26 [ vel eth0] 4 Ints/s (max: 11) >>> >>> With kernel v4.16-rc7 plus this patch series and tcb as clocksource: >>> >>> INT NAME RATE MAX >>> 17 [vel timer@fffa] 2164 Ints/s (max: 2183) >>> 26 [ vel eth0] 5 Ints/s (max: 10) >>> >>> Is this the information you wanted? If not, could you point me on how to get >>> the requested irq rate? >> >> It is perfect. Thanks! >> >> It confirms what I was worried about: the clocksource wraps up too >> quickly thus raising an interrupt every 400us. That is why I asked >> Alexande about a prescalar register. >> > > The code should behave exactly the same between the previous and the new > driver. The interrupt is not coming from the clocksource but from the > clockevent and it is already on the slowest clock, the 32kHz one. Do you have an explanation of why the rate is much higher ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog