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[209.132.180.67]) by mx.google.com with ESMTP id g4-v6si718415plb.522.2018.03.28.08.51.47; Wed, 28 Mar 2018 08:52:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754106AbeC1Pur (ORCPT + 99 others); Wed, 28 Mar 2018 11:50:47 -0400 Received: from mail.bootlin.com ([62.4.15.54]:38806 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753838AbeC1Pup (ORCPT ); Wed, 28 Mar 2018 11:50:45 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 3462920728; Wed, 28 Mar 2018 17:50:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id C9DC120146; Wed, 28 Mar 2018 17:50:32 +0200 (CEST) Date: Wed, 28 Mar 2018 17:50:33 +0200 From: Alexandre Belloni To: Daniel Lezcano Cc: Alexander Dahl , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Boris Brezillon , Thomas Gleixner Subject: Re: [PATCH v3 0/6] clocksource: rework Atmel TCB timer driver Message-ID: <20180328155033.GH13942@piout.net> References: <20180223171558.7037-1-alexandre.belloni@bootlin.com> <9761072.pX2B0LJlSJ@ada> <989df8a3-462a-c645-87f1-9f956e1b22c9@linaro.org> <4073350.0MmxRoANOi@ada> <6d43177a-bbea-6a01-5fa5-1c7891e18412@linaro.org> <20180328141645.GF13942@piout.net> <75e5917b-a9ba-c67e-e964-3f002681f9bb@linaro.org> <20180328153135.GG13942@piout.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180328153135.GG13942@piout.net> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/03/2018 at 17:31:35 +0200, Alexandre Belloni wrote: > > Do you have an explanation of why the rate is much higher ? > > > > The core is giving deltas of 31 clocks instead of much more than that, I > guess I messed up the initialization somewhere. > I did mess up. Alexander, can you test that: diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c index 7fde9cfbf203..bbbacf8c46b0 100644 --- a/drivers/clocksource/timer-atmel-tcb.c +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -222,7 +222,7 @@ static int __init tc_clkevt_register(struct device_node *node, goto err_slow; clk_disable(tce.clk); - clockevents_config_and_register(&tce.clkevt, 32768, 1, bits - 1); + clockevents_config_and_register(&tce.clkevt, 32768, 1, BIT(bits) - 1); ret = request_irq(tce.irq, tc_clkevt2_irq, IRQF_TIMER | IRQF_SHARED, tce.clkevt.name, &tce); This will behave exactly the same as before on 16bits TCB and will have much less interrupts on 32 bits platforms. -- Alexandre Belloni, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com