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[209.132.180.67]) by mx.google.com with ESMTP id u6-v6si6568669pld.628.2018.03.29.14.29.48; Thu, 29 Mar 2018 14:30:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=WonCPog6; dkim=pass header.i=@codeaurora.org header.s=default header.b=LPRr9JkG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752694AbeC2V2V (ORCPT + 99 others); Thu, 29 Mar 2018 17:28:21 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36272 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751189AbeC2V2S (ORCPT ); Thu, 29 Mar 2018 17:28:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B4874602FC; Thu, 29 Mar 2018 21:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522358897; bh=PHG08QjXd/65lpGvOT7FoTnt3bsMUy3g0u/BiCtOnHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WonCPog6sIrzaeEnczJzan1n2+KA9+34exZrCecQ2aXos7IEomhq4FzaA/SdgDfVD pPdG4YCefKaXVeTDQMGqIJSvJUmONMSK3V62EFA2rk5TeX2zKYUuDjWxU8iMRBTvni r3wxh1W3LlbQacD/+IRDgmiHWjFTz2oVIndaoZiY= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4FC4B61134; Thu, 29 Mar 2018 21:27:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522358883; bh=PHG08QjXd/65lpGvOT7FoTnt3bsMUy3g0u/BiCtOnHQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LPRr9JkGiM59KAnaf7BiJ/yWc+YZiyG3rDzN2IhLjU9B7BwSTj5MSfcpm1E3jhJpd ZTciuw8ubfibs/oS75KVQEGdIDJjzbv0mWYBi61eJcSlP+cHPadgEbw5JZ518oPrR6 7Gd6W3E+liLMBbTnbnLgz8M37WH2sz13QssoGmDE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4FC4B61134 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v4 11/14] dt: qcom: Add SAW regulator for 8x96 CPUs Date: Fri, 30 Mar 2018 00:26:44 +0300 Message-Id: <1522358807-10413-12-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522358807-10413-1-git-send-email-ilialin@codeaurora.org> References: <1522358807-10413-1-git-send-email-ilialin@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 1. Add syscon node for the SAW CPU registers 2. Add SAW regulators gang definition for s8-s11 3. Add voltages to the OPP tables 4. Add the s11 SAW regulator as CPU regulator Signed-off-by: Ilia Lin --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 77 +++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a0792bd..993f0a3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -15,6 +15,8 @@ #include #include #include +#include + / { model = "Qualcomm Technologies, Inc. MSM8996"; @@ -99,6 +101,7 @@ reg = <0x0 0x0>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; cooling-min-level = <0>; cooling-max-level = <15>; @@ -116,6 +119,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&kryocc 0>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster0_opp>; cooling-min-level = <0>; cooling-max-level = <15>; @@ -129,6 +133,7 @@ reg = <0x0 0x100>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; cooling-min-level = <0>; cooling-max-level = <15>; @@ -146,6 +151,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&kryocc 1>; + cpu-supply = <&pm8994_s11_saw>; operating-points-v2 = <&cluster1_opp>; cooling-min-level = <0>; cooling-max-level = <15>; @@ -182,66 +188,82 @@ opp-307200000 { opp-hz = /bits/ 64 < 307200000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 < 422400000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 < 480000000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 < 556800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 < 652800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 < 729600000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 < 844800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 < 960000000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 < 1036800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 < 1113600000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 < 1190400000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 < 1228800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 < 1324800000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 < 1401600000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 < 1478400000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 < 1593600000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; }; @@ -252,102 +274,127 @@ opp-307200000 { opp-hz = /bits/ 64 < 307200000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 < 403200000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 < 480000000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 < 556800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 < 652800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 < 729600000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 < 806400000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 < 883200000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 < 940800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 < 1036800000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 < 1113600000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 < 1190400000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 < 1248000000 >; + opp-microvolt = <905000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 < 1324800000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 < 1401600000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 < 1478400000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 < 1555200000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 < 1632000000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 < 1708800000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 < 1785600000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 < 1824000000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 < 1920000000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 < 1996800000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 < 2073600000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 < 2150400000 >; + opp-microvolt = <1140000 905000 1140000>; clock-latency-ns = <200000>; }; }; @@ -664,6 +711,11 @@ #mbox-cells = <1>; }; + saw3: syscon@9A10000 { + compatible = "syscon"; + reg = <0x9A10000 0x1000>; + }; + gcc: clock-controller@300000 { compatible = "qcom,gcc-msm8996"; #clock-cells = <1>; @@ -880,6 +932,31 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; + pmic@1 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + spm-regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <905000>; + regulator-max-microvolt = <1140000>; + }; + }; + }; }; mmcc: clock-controller@8c0000 { -- 1.9.1