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[209.132.180.67]) by mx.google.com with ESMTP id u6-v6si7684217pld.628.2018.03.30.01.23.05; Fri, 30 Mar 2018 01:23:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=rmocYm9n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751239AbeC3IU5 (ORCPT + 99 others); Fri, 30 Mar 2018 04:20:57 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:38342 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750995AbeC3IUx (ORCPT ); Fri, 30 Mar 2018 04:20:53 -0400 Received: by mail-wm0-f66.google.com with SMTP id l16so15629341wmh.3 for ; Fri, 30 Mar 2018 01:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=message-id:subject:from:to:cc:date:in-reply-to:references :mime-version:content-transfer-encoding; bh=R9xfHRkkwvAEUN0l8nZoP2lfeDaECLr6cGwL6Vk/B+4=; b=rmocYm9nI7YenrBepapm42X2z+f8vmH6EczaSOu514CEqprdNycvXjSSVVgTu7/akw 1Y1I8uU37tEg7sFKIxtqtw7wb8JtejHVD4bMh81v3ovXvrpnUGykpKYuM040DBCoJo51 i0TCMxajxs7O85P03Lbl9mTYKwPCusV3yvPArNPcAPYKVsXPU3z3soBNJfofU4WOj496 OxHFM4ES/GrIy7IrSSJjbjC3/GfsRvnMZzvHcGr+4WJO1BCtvfs96n6BgFNedVXLHinY IbgvUnSAeqfxuP9+bn1KGoBbzWGMEDeDnVv0/YvL3oHrwv8zGWznRR3xfHZz2uQwzD5c 2A1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:subject:from:to:cc:date:in-reply-to :references:mime-version:content-transfer-encoding; bh=R9xfHRkkwvAEUN0l8nZoP2lfeDaECLr6cGwL6Vk/B+4=; b=j+Zz6O1Ug1dyYvKLRKpJx+PY3POoYGysCWQ7CPRcIkmdwWaEFa3hOCzU78207KiKIF 5jbE5yQ50mjRE0Ztqbb12Y4FCmXmhHF2Dt/YigWq0aByuWtfnOroW7gSRMMLkSJ3w7hb +rJBMF0w2TMaLFui13TWx7/wXbKAc6E7mgWM5tsuwEZP8zucCyuL+MYbcEQSklcRU4GG Hit4fB94Il680tSpl2qaMuRqnULx4LVJGrT6MSW3Cv3H09e0emGxommrdQRScouIi/pm 4ABvJSGVD+J6UNHHrOMm2dkVTw74CORnws89IuZfQACCDffnkt7G5B7t/ky+WxNqHkYK 8ogQ== X-Gm-Message-State: AElRT7HvOj5Rybz22qstkm9812fDxEhmjzLJAzwyxeJePyddhAI5qQ7m feeDFjqCxXsixwqAPqEjX4TDew== X-Received: by 10.28.47.3 with SMTP id v3mr1664445wmv.96.1522398052535; Fri, 30 Mar 2018 01:20:52 -0700 (PDT) Received: from boomer ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id k14sm10597006wrc.62.2018.03.30.01.20.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Mar 2018 01:20:51 -0700 (PDT) Message-ID: <1522398050.3871.12.camel@baylibre.com> Subject: Re: [PATCH v5 08/10] clk: fix CLK_SET_RATE_GATE with clock rate protection From: Jerome Brunet To: Stephen Boyd , Michael Turquette Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King , Linus Walleij , Quentin Schulz , Kevin Hilman , Maxime Ripard Date: Fri, 30 Mar 2018 10:20:50 +0200 In-Reply-To: <20171201215200.23523-9-jbrunet@baylibre.com> References: <20171201215200.23523-1-jbrunet@baylibre.com> <20171201215200.23523-9-jbrunet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.6 (3.26.6-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2017-12-01 at 22:51 +0100, Jerome Brunet wrote: > Using clock rate protection, we can now enforce CLK_SET_RATE_GATE along the > clock tree Hi Mike, Stephen, Gentle ping. This patch has been waiting for while now. As far as I know, the only blocking point to merging this patch is the qcom mmc driver. The clocks used in this driver rely on the broken implementation of CLK_SET_RATE_GATE, effectively ignoring the flag. Since the flag is ignored, removing it from this particular clock won't make any difference. Can we just do that until a better fix is available for this qcom mmc clock ? --- A bit of history ---- I managed to have a run on kci - based on v4.12-rc6: https://kernelci.org/boot/all/job/khilman/branch/to-build/kernel/v4.12-rc6-10-ge a373ddef830/ There was no build regression but kci did find one boot regression on qcom platforms: * qcom-apq8064-cm-qs600 * qcom-apq8064-ifc6410 it seems the problem is coming from the clock used by the mmc driver (drivers/mmc/host/mmci.c) the driver does following sequence: * get_clk * prepare_enable * get_rate * set_rate * ... with clock SDCx_clk (qcom_apq8064.dtsi:1037). This clock has CLK_SET_RATE_PARENT flag so it will transmit the request to its parent. The parent of this clock is SDCx_src which has the CLK_SET_RATE_GATE flag. So obviously, is CLK_SET_RATE_GATE was enforced, the sequence used by mmci driver would never had worked. This particular driver rely on the fact that the clock can while the clock is on. Either it actually works and we can remove CLK_SET_RATE_GATE until a better solution comes. OR, it does not work which means nobody has been using this driver for a long time. > > Acked-by: Linus Walleij > Tested-by: Quentin Schulz > Tested-by: Maxime Ripard > Acked-by: Michael Turquette > Signed-off-by: Jerome Brunet > --- > drivers/clk/clk.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c > index f6fe5e5595ca..1af843ae20ff 100644 > --- a/drivers/clk/clk.c > +++ b/drivers/clk/clk.c > @@ -605,6 +605,9 @@ static void clk_core_unprepare(struct clk_core *core) > if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL)) > return; > > + if (core->flags & CLK_SET_RATE_GATE) > + clk_core_rate_unprotect(core); > + > if (--core->prepare_count > 0) > return; > > @@ -679,6 +682,16 @@ static int clk_core_prepare(struct clk_core *core) > > core->prepare_count++; > > + /* > + * CLK_SET_RATE_GATE is a special case of clock protection > + * Instead of a consumer claiming exclusive rate control, it is > + * actually the provider which prevents any consumer from making any > + * operation which could result in a rate change or rate glitch while > + * the clock is prepared. > + */ > + if (core->flags & CLK_SET_RATE_GATE) > + clk_core_rate_protect(core); > + > return 0; > unprepare: > clk_core_unprepare(core->parent); > @@ -1780,9 +1793,6 @@ static int clk_core_set_rate_nolock(struct clk_core *core, > if (clk_core_rate_is_protected(core)) > return -EBUSY; > > - if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count) > - return -EBUSY; > - > /* calculate new rates and get the topmost changed clock */ > top = clk_calc_new_rates(core, req_rate); > if (!top)