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[209.132.180.67]) by mx.google.com with ESMTP id d185si5764256pgc.746.2018.03.30.08.59.32; Fri, 30 Mar 2018 08:59:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=CjJOM5X2; dkim=pass header.i=@codeaurora.org header.s=default header.b=C6Dri34g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751897AbeC3P6V (ORCPT + 99 others); Fri, 30 Mar 2018 11:58:21 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57412 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751147AbeC3P6U (ORCPT ); Fri, 30 Mar 2018 11:58:20 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7DB8B60AE0; Fri, 30 Mar 2018 15:58:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522425499; bh=9P3nmIOtsheOIvw61tn3P+ezfFe0jYnK4uggoR11Q5o=; h=From:To:Cc:Subject:Date:From; b=CjJOM5X2Mzibt33NQ481IVBnskJsV1ySdFZHKps1JS+hv/t86hoU74q21p2gpg6Pm nFIPP7mO8poB9Xg2ErBuPb/roG7Jjt9I60ej//njpQSMttGlFtzKlOYqpRlxVX+n+y KB4Yj6kf/p0atkBeEzAAvGOGfFo8D/I+mxnR6GM4= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1566060588; Fri, 30 Mar 2018 15:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522425498; bh=9P3nmIOtsheOIvw61tn3P+ezfFe0jYnK4uggoR11Q5o=; h=From:To:Cc:Subject:Date:From; b=C6Dri34gKNggOrohnocdHIE5EDBGg8b2OhKMueJiKkY9n5VT2IwuaTriNxR0dKqmc ClxsId7bJHiVcRUqsdhUx0lv0aRjbriRrKDq3NaK+8dDU/WUjwMGpyyWPwqRk3bsU4 6HzgNpz7ZCkHBG/8UUHoIcGMxsbgp/sAns8ioeFA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1566060588 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] io: prevent compiler reordering on the default writeX() implementation Date: Fri, 30 Mar 2018 11:58:12 -0400 Message-Id: <1522425494-2916-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The default implementation of mapping writeX() to __raw_writeX() is wrong. writeX() has stronger ordering semantics. Compiler is allowed to reorder __raw_writeX(). In the abscence of a write barrier or when using a strongly ordered architecture, writeX() should at least have a compiler barrier in it to prevent commpiler from clobbering the execution order. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3..e8c2078 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -144,6 +144,7 @@ static inline u64 readq(const volatile void __iomem *addr) #define writeb writeb static inline void writeb(u8 value, volatile void __iomem *addr) { + barrier(); __raw_writeb(value, addr); } #endif @@ -152,6 +153,7 @@ static inline void writeb(u8 value, volatile void __iomem *addr) #define writew writew static inline void writew(u16 value, volatile void __iomem *addr) { + barrier(); __raw_writew(cpu_to_le16(value), addr); } #endif @@ -160,6 +162,7 @@ static inline void writew(u16 value, volatile void __iomem *addr) #define writel writel static inline void writel(u32 value, volatile void __iomem *addr) { + barrier(); __raw_writel(__cpu_to_le32(value), addr); } #endif @@ -169,6 +172,7 @@ static inline void writel(u32 value, volatile void __iomem *addr) #define writeq writeq static inline void writeq(u64 value, volatile void __iomem *addr) { + barrier(); __raw_writeq(__cpu_to_le64(value), addr); } #endif -- 2.7.4