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Date:   Mon, 2 Apr 2018 16:18:06 +0800
From:   Alan Kao <alankao@andestech.com>
To:     Alex Solomatnikov <sols@sifive.com>
CC:     Nick Hu <nickhu@andestech.com>, Jonathan Corbet <corbet@lwn.net>,
        "Peter Zijlstra" <peterz@infradead.org>,
        Palmer Dabbelt <palmer@sifive.com>,
        <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        "Arnaldo Carvalho de Melo" <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Ingo Molnar <mingo@redhat.com>,
        "Albert Ou" <albert@sifive.com>,
        Namhyung Kim <namhyung@kernel.org>,
        <linux-riscv@lists.infradead.org>, Jiri Olsa <jolsa@redhat.com>,
        Greentime Hu <greentime@andestech.com>
Subject: Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support
Message-ID: <20180402081806.GA24954@andestech.com>
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Hi Alex,
 
On Mon, Apr 02, 2018 at 03:36:12PM +0800, Alan Kao wrote:
> On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
> 
> The original guess was that maybe, an counter value on a hart is picked
> as the minusend, and an old counter value on another hart was recorded
> as the subtrahend but numerically larger.  Then, the overflow causes 
> by that subtraction.  Please let me name this guess as 
> "cross-hart subtraction."
>
> > You can add a skew between cores in qemu, something like this:
> > 
> > case CSR_INSTRET:
> >         core_id()*return cpu_get_host_ticks()/10;
> >     break;
> > case CSR_CYCLE:
> >         return cpu_get_host_ticks();
> >     break;
> > 
> 
> However, I tried similar stuff to reproduce the phenomenon but in vain.
> It seems that the 
>
>               ***cross-hart subtration doesn't even happen, because generic
> code handles them.  ...

I am sorry that this observation is wrong.  With appropriate tweak, we
successfully reproduce the behavior and locate the the bug.

This will be fix in v2.


Thanks for the helps.
Alan