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[74.125.82.41]) by smtp.gmail.com with ESMTPSA id s10sm1306056edc.63.2018.04.02.23.45.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Apr 2018 23:45:47 -0700 (PDT) Received: by mail-wm0-f41.google.com with SMTP id v21so30866895wmc.1; Mon, 02 Apr 2018 23:45:47 -0700 (PDT) X-Received: by 10.28.135.195 with SMTP id j186mr3261438wmd.143.1522737946854; Mon, 02 Apr 2018 23:45:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.164.129 with HTTP; Mon, 2 Apr 2018 23:45:26 -0700 (PDT) In-Reply-To: <20180403061836.3926-5-mylene.josserand@bootlin.com> References: <20180403061836.3926-1-mylene.josserand@bootlin.com> <20180403061836.3926-5-mylene.josserand@bootlin.com> From: Chen-Yu Tsai Date: Tue, 3 Apr 2018 14:45:26 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 04/13] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi To: =?UTF-8?Q?Myl=C3=A8ne_Josserand?= Cc: Russell King , Maxime Ripard , Marc Zyngier , Mark Rutland , Rob Herring , devicetree , LABBE Corentin , quentin.schulz@bootlin.com, Thomas Petazzoni , linux-arm-kernel , linux-kernel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 3, 2018 at 2:18 PM, Mylène Josserand wrote: > As we found in sun9i-a80, CPUCFG is a collection of registers that are > mapped to the SoC's signals from each individual processor core and > associated peripherals. > > These registers are used for SMP bringup and CPU hotplugging. > > Signed-off-by: Mylène Josserand Reviewed-by: Chen-Yu Tsai