Received: by 10.213.65.68 with SMTP id h4csp534705imn; Wed, 4 Apr 2018 02:54:48 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+9j8Bdkq0BBncY0Wwi+Mq/ruJf9Frf1HFG6Q+bROhvywGM8MBTH49G4yl2n3X3fvVdpe1n X-Received: by 10.101.85.200 with SMTP id k8mr7517852pgs.290.1522835688304; Wed, 04 Apr 2018 02:54:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522835688; cv=none; d=google.com; s=arc-20160816; b=QvLiFhkSZLL6MzJUiSnqhUzQQkQgkSwndJdlZi/MASYg2ryujbc4kyBljHLeSmV6va zvlqgql/CKlC+5l5kJ+nwj+5tyICC14RADEFMxOkGYhJKD9lLMtCrxfnNWPphDKvGiW4 2MBbtQicVEDQSaShLAoiqALBlfop4vIhHpcegpMJsHQQxE+ETsz4OvisMNlLaFUcHmQy gUzymjQvk6FoTAxVIktv23mK6sYUBrfed4FBqlOG/rqwVOhRQ1o0f5WCkhVzsP0h3y/c GP32hyeKSKvfm8ZzP6nEV2lokB16i00HcAUoImMJPVr3EyQK9AJyr0K9TE6fGdsP24MT Sjrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=EsArHuS3zmwW+xgMsxgaCRTIRkE5QsrspR8MEWBQ6Bo=; b=nmc4cToF7pprNTrKMYu/rGX2ZmWd0p9k/Gqg2agc3+apD7oMGxjbrvHufLIdSTC10k EHcWBP+NZztnd+iWPbhnA3sx8/Tc1f/fvPgpxTjpsxuvnAnHjOgRStez3S4QPraYfIbr CrZWHmkStMQAn4ZPKrzf2Y1Qta1+re/RffngEfX5zDpY3PToJwVEY4l3vzLviy9EwPtA Ao9Rd2OZY7jPSYQtKT1S0fg0FxcpLzy+bnEM+V2cl3Wg5vYy0ixyWnA+7awrok77N08Z wCn6epk4tXiG2ATiMbYSAy2L5J+40wPaXtBP/ndcpX/7ZL3qVrfK8pBtgaa8gynXtO4I MsEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v10-v6si717416ply.74.2018.04.04.02.54.34; Wed, 04 Apr 2018 02:54:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751098AbeDDJxJ (ORCPT + 99 others); Wed, 4 Apr 2018 05:53:09 -0400 Received: from zxshcas1.zhaoxin.com ([180.169.121.91]:59221 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750736AbeDDJxH (ORCPT ); Wed, 4 Apr 2018 05:53:07 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Wed, 4 Apr 2018 17:53:03 +0800 Received: from timguo-System-Product-Name.zhaoxin.com (10.29.8.54) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Wed, 4 Apr 2018 17:53:02 +0800 From: David Wang To: , , , , , CC: , , , , , , David Wang Subject: [PATCH] x86/centaur: report correct CPU/cache topology Date: Wed, 4 Apr 2018 17:52:59 +0800 Message-ID: <1522835579-22893-1-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.54] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch is used to support multi-core Centaur CPU. After using this patch, we can get correct CPU topology and correct cache topology. Signed-off-by: David Wang --- arch/x86/kernel/cpu/centaur.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index e5ec0f1..713e4db 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -112,6 +112,19 @@ static void early_init_centaur(struct cpuinfo_x86 *c) } } +static int centaur_num_cpu_cores(struct cpuinfo_x86 *c) +{ + unsigned int eax, ebx, ecx, edx; + + if (c->cpuid_level < 4) + return 1; + cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); + if (eax & 0x1f) + return (eax >> 26) + 1; + else + return 1; +} + static void init_centaur(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_32 @@ -128,6 +141,13 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + + init_intel_cacheinfo(c); + c->x86_max_cores = centaur_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif + switch (c->x86) { #ifdef CONFIG_X86_32 case 5: -- 1.9.1