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[209.132.180.67]) by mx.google.com with ESMTP id r9si4052056pfg.8.2018.04.04.05.47.31; Wed, 04 Apr 2018 05:47:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bsGvHmsL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752059AbeDDMpb (ORCPT + 99 others); Wed, 4 Apr 2018 08:45:31 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:42592 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751813AbeDDMp0 (ORCPT ); Wed, 4 Apr 2018 08:45:26 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w34CiCwZ012823; Wed, 4 Apr 2018 07:44:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1522845852; bh=Lb9xPyM/RB4QhKU4aK40ZWWOdLSojPStC1qy0p6G8Hk=; h=Subject:From:To:CC:References:Date:In-Reply-To; b=bsGvHmsLrdCNC7wutqjVH5qrBWAoQTmsbli3AqYnKt8Sd8A1+517EURGnS7ZGWq3V jQ2U8MUxi/sHBl6cSSJu2AtUMkbA2OazaRnq5cv8syUde6aUHbRLLEfqAtlryuPuYW bpHwPdWi/C7jLCGLhs7PudGiBBU2tHvBnk89Jwdg= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w34CiCxx003988; Wed, 4 Apr 2018 07:44:12 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Wed, 4 Apr 2018 07:44:12 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Wed, 4 Apr 2018 07:44:12 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w34Ci8uj010601; Wed, 4 Apr 2018 07:44:09 -0500 Subject: Re: [PATCH v8 25/42] ARM: davinci: dm644x: add new clock init using common clock framework From: Sekhar Nori To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <1521168778-27236-1-git-send-email-david@lechnology.com> <1521168778-27236-26-git-send-email-david@lechnology.com> <333f49c7-bafd-8e2d-65e9-7d1aff4836de@ti.com> <43c266b8-c023-a1b4-c751-bd46c2fb910d@lechnology.com> Message-ID: <030ce534-765b-3059-a6a1-fffaaaba307a@ti.com> Date: Wed, 4 Apr 2018 18:14:07 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 04 April 2018 12:17 PM, Sekhar Nori wrote: > On Tuesday 03 April 2018 10:00 PM, David Lechner wrote: >> On 04/03/2018 05:26 AM, Sekhar Nori wrote: >>> On Friday 16 March 2018 08:22 AM, David Lechner wrote: >>>> +static struct resource dm644x_pll1_resources[] = { >>>> +    { >>>> +        .start    = DAVINCI_PLL1_BASE, >>>> +        .end    = DAVINCI_PLL1_BASE + SZ_4K - 1, >>> >>> The .end should be DAVINCI_PLL1_BASE + SZ_1K - 1, otherwise it prevents >>> PLL2 from getting registered. >>> >>>> +        .flags    = IORESOURCE_MEM, >>>> +    }, >>>> +}; >>>> + >>>> +static struct platform_device dm644x_pll1_device = { >>>> +    .name        = "dm644x-pll1", >>>> +    .id        = -1, >>>> +    .resource    = dm644x_pll1_resources, >>>> +    .num_resources    = ARRAY_SIZE(dm644x_pll1_resources), >>>> +}; >>>> + >>>> +static struct resource dm644x_pll2_resources[] = { >>>> +    { >>>> +        .start    = DAVINCI_PLL2_BASE, >>>> +        .end    = DAVINCI_PLL2_BASE + SZ_4K - 1, >>> >>> And this too should be fixed, else it prevents the PSC from getting >>> registered. >>> >>>> +        .flags    = IORESOURCE_MEM, >>>> +    }, >>>> +}; >>> >>> With these fixed, I still had to enable 'clk_ignore_unused' on DM644x >>> EVM to get to NFS boot. I think root of the problem is that pm_runtime() >>> APIs are not working in the legacy boot mode. >>> >>> This can be seen even on the DA850 LCDK in legacy boot. pm_genpd_summary >>> in debugfs shows all domains are off and there are no devices registered >>> under the "da850-psc1: emac" domain. NFS mounting still works on the >>> DA850 LCDK because clk_summary shows enable and prepare count of 4 for >>> emac. Not sure how that's happening. But on DM644x EVM, the emac clock >>> enable count is 0. >>> >>> Still looking at whats going wrong here. I am testing your v8 branch >>> with clk-davinci branch from clk-next merged to get the fixes Stephen >>> made. >>> >> >> In legacy mode, genpd is not being used. I didn't see any mechanism for > > Ah, I got stumped by the genpd related debug entries popping up. > Probably something should be done to make sure they don't show up in > legacy boot. And some comments to that effect in psc.c will help. > >> genpd lookup without device tree. So, we are still relying on the >> matching in arch/arm/mach-davinci/pm_domain.c. > > This is fine. We just need legacy boot to keep working without regressions. > >> >> I suspect we need to fix the clock lookups in >> drivers/clk/davinci/psc-dm644x.c. >> >> LPSC_CLKDEV2(emac_clkdev,        NULL,        "davinci_emac.1", >>                     "fck",        "davinci_mdio.0"); >> >> NULL might need to be changed to "fck" to be picked up by pm matching >> and "davinci_emac.1" should be verified that it matches the actual EMAC >> device name. > > NULL con_id matches what we have for DA850 and also what we had for > DM644x prior to CCF conversion. So, I did not really suspect that. The > device name does match. I will check what else could be going on based > on your input. This issue is because emac platform device is getting registered really early on dm644x even before the clocks are ready in postcore_initcall(). I will send a patch fixing that. Thanks, Sekhar