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[209.132.180.67]) by mx.google.com with ESMTP id u14si4514773pgq.103.2018.04.04.16.59.40; Wed, 04 Apr 2018 17:00:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=Tx9BIi2z; dkim=pass header.i=@codeaurora.org header.s=default header.b=Tx9BIi2z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752721AbeDDX6e (ORCPT + 99 others); Wed, 4 Apr 2018 19:58:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35548 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752628AbeDDX63 (ORCPT ); Wed, 4 Apr 2018 19:58:29 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id ABC50602BA; Wed, 4 Apr 2018 23:58:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886308; bh=o8TjFDYwffhmWD4rbtWynHXU54myXkNL915S7Ew1PF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tx9BIi2zgBlMFu7xAZMHKHxFAqnPpPamhrK3bVZI3p6nn7DNlNrm1YF7NftEBWklE wxOuxXIRtahwgJ1I6VY6Qd0z3lI/a9ZL3MSTlznue9mpleVVwC9Vruky67nqNna/6U wm91ua93EKv8mh0SusyGeBB9Ac4NYyFJeQyZCAKM= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7BD0360F6E; Wed, 4 Apr 2018 23:58:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886308; bh=o8TjFDYwffhmWD4rbtWynHXU54myXkNL915S7Ew1PF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tx9BIi2zgBlMFu7xAZMHKHxFAqnPpPamhrK3bVZI3p6nn7DNlNrm1YF7NftEBWklE wxOuxXIRtahwgJ1I6VY6Qd0z3lI/a9ZL3MSTlznue9mpleVVwC9Vruky67nqNna/6U wm91ua93EKv8mh0SusyGeBB9Ac4NYyFJeQyZCAKM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7BD0360F6E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] io: define stronger ordering for the default writeX() implementation Date: Wed, 4 Apr 2018 19:58:18 -0400 Message-Id: <1522886301-25955-3-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> References: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The default implementation of mapping writeX() to __raw_writeX() is wrong. writeX() has stronger ordering semantics. Compiler is allowed to reorder memory writes against __raw_writeX(). Use the previously defined __io_aw() and __io_bw() macros to harden code generation according to architecture support. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index fc554af..ca268d9 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -207,7 +207,9 @@ static inline u64 readq(const volatile void __iomem *addr) #define writeb writeb static inline void writeb(u8 value, volatile void __iomem *addr) { + __io_bw(); __raw_writeb(value, addr); + __io_aw(); } #endif @@ -215,7 +217,9 @@ static inline void writeb(u8 value, volatile void __iomem *addr) #define writew writew static inline void writew(u16 value, volatile void __iomem *addr) { + __io_bw(); __raw_writew(cpu_to_le16(value), addr); + __io_aw(); } #endif @@ -223,7 +227,9 @@ static inline void writew(u16 value, volatile void __iomem *addr) #define writel writel static inline void writel(u32 value, volatile void __iomem *addr) { + __io_bw(); __raw_writel(__cpu_to_le32(value), addr); + __io_aw(); } #endif @@ -232,7 +238,9 @@ static inline void writel(u32 value, volatile void __iomem *addr) #define writeq writeq static inline void writeq(u64 value, volatile void __iomem *addr) { + __io_bw(); __raw_writeq(__cpu_to_le64(value), addr); + __io_aw(); } #endif #endif /* CONFIG_64BIT */ -- 2.7.4