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[209.132.180.67]) by mx.google.com with ESMTP id v45si4522870pgn.379.2018.04.04.17.00.27; Wed, 04 Apr 2018 17:00:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=a7Y5VLf3; dkim=pass header.i=@codeaurora.org header.s=default header.b=a7Y5VLf3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752672AbeDDX6b (ORCPT + 99 others); Wed, 4 Apr 2018 19:58:31 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35398 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752622AbeDDX60 (ORCPT ); Wed, 4 Apr 2018 19:58:26 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D715B6081B; Wed, 4 Apr 2018 23:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886305; bh=smBaDU/Vj6uQZfMoFzr0Mu3kbyqaCc4TK0NtnqObLTE=; h=From:To:Cc:Subject:Date:From; b=a7Y5VLf3M2P7FCrbXmh9K81PF9MmRx+v9UPyIRj5gTMwcqoCmuKzVZ/a9h1UnfSX8 AjzQIHSISR0ANZDLiXNVM4LVqhPhfGpCJtTWDQrKI/JLjcM/a89bt0Ni31RdeTGb8r AuYtB5XDIGv/R8vmYL/s+l0oZbPZukedVM1yii6g= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A913060364; Wed, 4 Apr 2018 23:58:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886305; bh=smBaDU/Vj6uQZfMoFzr0Mu3kbyqaCc4TK0NtnqObLTE=; h=From:To:Cc:Subject:Date:From; b=a7Y5VLf3M2P7FCrbXmh9K81PF9MmRx+v9UPyIRj5gTMwcqoCmuKzVZ/a9h1UnfSX8 AjzQIHSISR0ANZDLiXNVM4LVqhPhfGpCJtTWDQrKI/JLjcM/a89bt0Ni31RdeTGb8r AuYtB5XDIGv/R8vmYL/s+l0oZbPZukedVM1yii6g= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A913060364 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/5] io: define several IO & PIO barrier types for the asm-generic version Date: Wed, 4 Apr 2018 19:58:16 -0400 Message-Id: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Getting ready to harden readX()/writeX() and inX()/outX() semantics for the generic implementation. Defining two set of macros as __io_br() and __io_ar() to indicate actions to be taken before and after MMIO read. Defining two set of macros as __io_bw() and __io_aw() to indicate actions to be taken before and after MMIO write. Defining two set of macros as __io_pbw() and __io_paw() to indicate actions to be taken before and after Port IO write. Defining two set of macros as __io_pbr() and __io_par() to indicate actions to be taken before and after Port IO read. If rmb() is available for the architecture, prefer rmb() as the default implementation of __io_ar()/__io_par(). If wmb() is available for the architecture, prefer wmb() as the default implementation of __io_bw()/__io_pbw(). Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index b4531e3..a3d349e 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -25,6 +25,49 @@ #define mmiowb() do {} while (0) #endif +#ifndef __io_br +#define __io_br() barrier() +#endif + +#ifndef __io_ar +#ifdef rmb +/* prefer rmb() as the default implementation of __io_ar() if supported */ +#define __io_ar() rmb() +#else +#define __io_ar() barrier() +#endif +#endif + +#ifndef __io_bw +#ifdef wmb +/* prefer wmb() as the default implementation of __io_bw() if supported */ +#define __io_bw() wmb() +#else +#define __io_bw() barrier() +#endif +#endif + +#ifndef __io_aw +#define __io_aw() barrier() +#endif + +#ifndef __io_pbw +#define __io_pbw() __io_bw() +#endif + +#ifndef __io_paw +#define __io_paw() __io_aw() +#endif + +#ifndef __io_pbr +#define __io_pbr() __io_br() +#endif + +#ifndef __io_par +#define __io_par() __io_ar() +#endif + + /* * __raw_{read,write}{b,w,l,q}() access memory in native endianness. * -- 2.7.4