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[209.132.180.67]) by mx.google.com with ESMTP id r26si4578926pgu.422.2018.04.04.17.00.47; Wed, 04 Apr 2018 17:01:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=BRJjZJhv; dkim=pass header.i=@codeaurora.org header.s=default header.b=BRJjZJhv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752831AbeDDX7S (ORCPT + 99 others); Wed, 4 Apr 2018 19:59:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35512 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752484AbeDDX62 (ORCPT ); Wed, 4 Apr 2018 19:58:28 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AAA7960F5F; Wed, 4 Apr 2018 23:58:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886307; bh=jhdiuMUmJFP4I9h+cUKJPsPYYFLcdWKoXaa3tFF3M+Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BRJjZJhvIQXUQl0vtAbl2XBYVGzkHe5zgcfGqHBW6i9iLjUPoxYarH37i5W9aGLtq ZjOx0ReBbC2xo6Y3zmETmVHHyPwKht6JRIdWwCJ7x7wkgrZDIEHPMq2G1imgJrRzAj LioXC1fDebeNiV11nXHkw+oV7T2pNyWlVPPXOQV0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3D2D660F5F; Wed, 4 Apr 2018 23:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522886307; bh=jhdiuMUmJFP4I9h+cUKJPsPYYFLcdWKoXaa3tFF3M+Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BRJjZJhvIQXUQl0vtAbl2XBYVGzkHe5zgcfGqHBW6i9iLjUPoxYarH37i5W9aGLtq ZjOx0ReBbC2xo6Y3zmETmVHHyPwKht6JRIdWwCJ7x7wkgrZDIEHPMq2G1imgJrRzAj LioXC1fDebeNiV11nXHkw+oV7T2pNyWlVPPXOQV0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3D2D660F5F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/5] io: define stronger ordering for the default readX() implementation Date: Wed, 4 Apr 2018 19:58:17 -0400 Message-Id: <1522886301-25955-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> References: <1522886301-25955-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX() against the memory accesses following register read. Use the previously defined __io_ar() and __io_br() macros to harden code generation according to architecture support. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index a3d349e..fc554af 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -153,7 +153,12 @@ static inline void __raw_writeq(u64 value, volatile void __iomem *addr) #define readb readb static inline u8 readb(const volatile void __iomem *addr) { - return __raw_readb(addr); + u8 val; + + __io_br(); + val = __raw_readb(addr); + __io_ar(); + return val; } #endif @@ -161,7 +166,12 @@ static inline u8 readb(const volatile void __iomem *addr) #define readw readw static inline u16 readw(const volatile void __iomem *addr) { - return __le16_to_cpu(__raw_readw(addr)); + u16 val; + + __io_br(); + val = __le16_to_cpu(__raw_readw(addr)); + __io_ar(); + return val; } #endif @@ -169,7 +179,12 @@ static inline u16 readw(const volatile void __iomem *addr) #define readl readl static inline u32 readl(const volatile void __iomem *addr) { - return __le32_to_cpu(__raw_readl(addr)); + u32 val; + + __io_br(); + val = __le32_to_cpu(__raw_readl(addr)); + __io_ar(); + return val; } #endif @@ -178,7 +193,12 @@ static inline u32 readl(const volatile void __iomem *addr) #define readq readq static inline u64 readq(const volatile void __iomem *addr) { - return __le64_to_cpu(__raw_readq(addr)); + u64 val; + + __io_br(); + val = __le64_to_cpu(__raw_readq(addr)); + __io_ar(); + return val; } #endif #endif /* CONFIG_64BIT */ -- 2.7.4