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[209.132.180.67]) by mx.google.com with ESMTP id f2-v6si5613432plo.434.2018.04.05.04.32.33; Thu, 05 Apr 2018 04:32:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hdTKSZGD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751483AbeDELbP (ORCPT + 99 others); Thu, 5 Apr 2018 07:31:15 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:15716 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751285AbeDELbN (ORCPT ); Thu, 5 Apr 2018 07:31:13 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w35BU87i027831; Thu, 5 Apr 2018 06:30:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1522927808; bh=JCQZmRLWRayYcOUeekQpOzAP/uJmKj6k6/BWXHw95Ug=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=hdTKSZGD2e9BmY0hdO0ASfoudnaGEX3sCDSaUxlJYDy8+A6JbGOcWjUd3jfYBvZac 8YZCTdfBLusyS0j+HcC8k/M4V6NRvl0HswS6xdR/2d8WFJ8O1qRVVNLCkJRh1w6CtN oW1zKwLVC9gELKCf7QCdIopFYRI0qJb1rVt0Yp1w= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w35BU8EC026286; Thu, 5 Apr 2018 06:30:08 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 5 Apr 2018 06:30:08 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 5 Apr 2018 06:30:08 -0500 Received: from [172.24.190.172] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w35BU1Ej001873; Thu, 5 Apr 2018 06:30:02 -0500 Subject: Re: [PATCH v8 40/42] ARM: davinci: add device tree support to timer To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <1521168778-27236-1-git-send-email-david@lechnology.com> <1521168778-27236-41-git-send-email-david@lechnology.com> From: Sekhar Nori Message-ID: <205cae72-4e91-aca2-e3b2-829a12066dc8@ti.com> Date: Thu, 5 Apr 2018 17:00:01 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1521168778-27236-41-git-send-email-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 16 March 2018 08:22 AM, David Lechner wrote: > +static int __init of_davinci_timer_init(struct device_node *np) > +{ > + struct clk *clk; > + > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + struct of_phandle_args clkspec; > + > + /* > + * Fall back to using ref_clk if the actual clock is not > + * available. This currently always happens because platform > + * clocks (i.e PLLs and PSCs) are registered as platform > + * devices and therefore are not available at this point in > + * the boot process. It seems to me that this is not going to be a temporary problem (or at least will be around for quite a while). So, I think we can as well just look for ref_clk directly. > + */ > + clkspec.np = of_find_node_by_name(NULL, "ref_clk"); > + if (IS_ERR(clkspec.np)) { > + pr_err("%s: No clock available for timer!\n", __func__); > + return PTR_ERR(clkspec.np); > + } > + clk = of_clk_get_from_provider(&clkspec); > + of_node_put(clkspec.np); > + } > + > + davinci_timer_init(clk); > + > + return 0; > +} > +TIMER_OF_DECLARE(davinci_timer, "ti,davinci-timer", of_davinci_timer_init); Here, I think we should use "ti,da850-timer" so we can change the fixed clock we are looking for based on the SoC. At a minimum, we should have "ti,da850-timer" in the DT along with "ti,davinci-timer". BTW, I noticed that "ti,davinci-timer" is not documented. I think we need to add a binding documentation too. Thanks, Sekhar