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[209.132.180.67]) by mx.google.com with ESMTP id c6si6134654pfl.136.2018.04.05.06.10.53; Thu, 05 Apr 2018 06:11:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=MItZrKYh; dkim=pass header.i=@codeaurora.org header.s=default header.b=MItZrKYh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751494AbeDENJY (ORCPT + 99 others); Thu, 5 Apr 2018 09:09:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:38270 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751326AbeDENJV (ORCPT ); Thu, 5 Apr 2018 09:09:21 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AAE35602BA; Thu, 5 Apr 2018 13:09:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522933760; bh=TrUjjxVR/fVeUr5VZx/A4eiHPXNISJFVDR0e/T7eb3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MItZrKYhSZzDAfmVXIGqQvtMr8cUtNxrvEo2JD2gzLjmyQucv5wmHMndcVtZXpW7R pBoVsGnuwUo1jFCS1GH7c7Qd97z5qDm1mA830fchTRenU7uym+Nojf3ks2SaHFPzDt 3grBwGai8pMEV6k7DtIxv6QVltJsI+rOS9zG/xY8= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7823460850; Thu, 5 Apr 2018 13:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522933760; bh=TrUjjxVR/fVeUr5VZx/A4eiHPXNISJFVDR0e/T7eb3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MItZrKYhSZzDAfmVXIGqQvtMr8cUtNxrvEo2JD2gzLjmyQucv5wmHMndcVtZXpW7R pBoVsGnuwUo1jFCS1GH7c7Qd97z5qDm1mA830fchTRenU7uym+Nojf3ks2SaHFPzDt 3grBwGai8pMEV6k7DtIxv6QVltJsI+rOS9zG/xY8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7823460850 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: arnd@arndb.de, timur@codeaurora.org, sulrich@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/5] io: define stronger ordering for the default readX() implementation Date: Thu, 5 Apr 2018 09:09:10 -0400 Message-Id: <1522933753-19589-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522933753-19589-1-git-send-email-okaya@codeaurora.org> References: <1522933753-19589-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX() against the memory accesses following register read. Use the previously defined __io_ar() and __io_br() macros to harden code generation according to architecture support. Signed-off-by: Sinan Kaya --- include/asm-generic/io.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 570433b..d27e8af 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -154,7 +154,12 @@ static inline void __raw_writeq(u64 value, volatile void __iomem *addr) #define readb readb static inline u8 readb(const volatile void __iomem *addr) { - return __raw_readb(addr); + u8 val; + + __io_br(); + val = __raw_readb(addr); + __io_ar(); + return val; } #endif @@ -162,7 +167,12 @@ static inline u8 readb(const volatile void __iomem *addr) #define readw readw static inline u16 readw(const volatile void __iomem *addr) { - return __le16_to_cpu(__raw_readw(addr)); + u16 val; + + __io_br(); + val = __le16_to_cpu(__raw_readw(addr)); + __io_ar(); + return val; } #endif @@ -170,7 +180,12 @@ static inline u16 readw(const volatile void __iomem *addr) #define readl readl static inline u32 readl(const volatile void __iomem *addr) { - return __le32_to_cpu(__raw_readl(addr)); + u32 val; + + __io_br(); + val = __le32_to_cpu(__raw_readl(addr)); + __io_ar(); + return val; } #endif @@ -179,7 +194,12 @@ static inline u32 readl(const volatile void __iomem *addr) #define readq readq static inline u64 readq(const volatile void __iomem *addr) { - return __le64_to_cpu(__raw_readq(addr)); + u64 val; + + __io_br(); + val = __le64_to_cpu(__raw_readq(addr)); + __io_ar(); + return val; } #endif #endif /* CONFIG_64BIT */ -- 2.7.4