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[209.132.180.67]) by mx.google.com with ESMTP id j23si6045611pgn.231.2018.04.05.13.52.43; Thu, 05 Apr 2018 13:52:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751417AbeDEUuC (ORCPT + 99 others); Thu, 5 Apr 2018 16:50:02 -0400 Received: from mail-qt0-f194.google.com ([209.85.216.194]:32804 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751155AbeDEUuA (ORCPT ); Thu, 5 Apr 2018 16:50:00 -0400 Received: by mail-qt0-f194.google.com with SMTP id d50so21012900qtc.0 for ; Thu, 05 Apr 2018 13:49:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:subject:from:to:cc:date:in-reply-to :references:organization:mime-version:content-transfer-encoding; bh=8iEx7hH3whAz9fQOUCOTut4Spjv6u3oiprCnhu1hFEk=; b=KEJNQ5gkclV2CwdWd3T0ZZlCDRG+WO7lB6MhRb+cmpZTJPp7DNeTMASb1bvrssm8b2 Y86knnnlMe4NcYeRaRsnAdvDPE+Jz0m3mxeA7ZayZ0Zq4UogX54RL9skTEKZmW27agn2 sw4hQy4HKfFZYVIF5m2m7kKsakmjtcUi9AAvrXfe6mckUn0eGThZqbyzRgm0w5z5UvPw ZTQY8yDh4w13zAtWjnLwIzgdTA9M13wc3wL3WSGb+nkxSqfbThtjEGvJTSXN4yNbEAG5 BbZEGhe2/d83aG7iqa23O/i2aJnxb2V5IhB/oTkN/Xnaezbh7yViy/zida4TGChnMYgq oSQQ== X-Gm-Message-State: ALQs6tCUJ+1plO7Q2LOvT4aLI3mqplFEJe+ISSQ1nyjeB4/orrGyVGxW rpff4KSBPm95jjyXfQQMXaw1qA== X-Received: by 10.200.114.195 with SMTP id o3mr30372572qtp.112.1522961399492; Thu, 05 Apr 2018 13:49:59 -0700 (PDT) Received: from dhcp-10-20-1-55.bss.redhat.com ([144.121.20.162]) by smtp.gmail.com with ESMTPSA id n58sm7180038qta.34.2018.04.05.13.49.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 05 Apr 2018 13:49:59 -0700 (PDT) Message-ID: <1522961397.4019.0.camel@redhat.com> Subject: Re: [PATCH v2] drm/i915/dp: Send DPCD ON for MST before phy_up From: Lyude Paul To: intel-gfx@lists.freedesktop.org Cc: Dhinakaran Pandiyan , Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= , Laura Abbott , stable@vger.kernel.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Thu, 05 Apr 2018 16:49:57 -0400 In-Reply-To: <20180405203601.23242-1-lyude@redhat.com> References: <20180405203601.23242-1-lyude@redhat.com> Organization: Red Hat Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.6 (3.26.6-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Actually - ignore this patch, I'm going to do a v3 because i just noticed there is something very silly and broken I just introduced into the disable codepath On Thu, 2018-04-05 at 16:36 -0400, Lyude Paul wrote: > When doing a modeset where the sink is transitioning from D3 to D0 , it > would sometimes be possible for the initial power_up_phy() to start > timing out. This would only be observed in the last action before the > sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We > originally thought this might be an issue with us accidentally shutting > off the aux block when putting the sink into D3, but since the DP spec > mandates that sinks must wake up within 1ms while we have 100ms to > respond to an ESI irq, this didn't really add up. Turns out that the > problem is more subtle then that: > > It turns out that the timeout is from us not enabling DPMS on the MST > hub before actually trying to initiate sideband communications. This > would cause the first sideband communication (power_up_phy()), to start > timing out because the sink wasn't ready to respond. Afterwards, we > would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in > intel_ddi_pre_enable_dp(), which would actually result in waking up the > sink so that sideband requests would work again. > > Since DPMS is what lets us actually bring the hub up into a state where > sideband communications become functional again, we just need to make > sure to enable DPMS on the display before attempting to perform sideband > communications. > > Changes since v1: > - Remove comment above if (!intel_dp->is_mst) - vsryjala > - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to > keep enable/disable paths symmetrical > - Improve commit message - dhnkrn > > Signed-off-by: Lyude Paul > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjälä > Cc: Laura Abbott > Cc: stable@vger.kernel.org > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST > hub.") > --- > This email should hopefully actually be picked up by patchwork this > time, hooray! > > drivers/gpu/drm/i915/intel_ddi.c | 6 ++++-- > drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++ > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index a6672a9abd85..c0bf7419e1c1 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct > intel_encoder *encoder, > intel_prepare_dp_ddi_buffers(encoder, crtc_state); > > intel_ddi_init_dp_buf_reg(encoder); > - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > + if (!intel_dp->is_mst) > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > intel_dp_start_link_train(intel_dp); > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) > intel_dp_stop_link_train(intel_dp); > @@ -2427,7 +2428,8 @@ static void intel_ddi_post_disable_dp(struct > intel_encoder *encoder, > * Power down sink before disabling the port, otherwise we end > * up getting interrupts from the sink on detecting link loss. > */ > - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); > + if (!intel_dp->is_mst) > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); > > intel_disable_ddi_buf(encoder); > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c > b/drivers/gpu/drm/i915/intel_dp_mst.c > index c3de0918ee13..2493bd1e0e59 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -176,6 +176,7 @@ static void intel_mst_post_disable_dp(struct > intel_encoder *encoder, > */ > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, > false); > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); > > intel_dp->active_mst_links--; > > @@ -223,6 +224,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder > *encoder, > > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); > > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, > true); > if (intel_dp->active_mst_links == 0) > intel_dig_port->base.pre_enable(&intel_dig_port->base, -- Cheers, Lyude Paul