Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   "liwei (CM)" <liwei213@huawei.com>
To:     Shawn Lin <shawn.lin@rock-chips.com>,
        Ryan Grachek <ryan@edited.us>,
        "Jinguojun (A)" <kid.jin@hisilicon.com>,
        "jingbing (C)" <jingbing2@hisilicon.com>
CC:     Jaehoon Chung <jh80.chung@samsung.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Zhangfei Gao <zhangfei.gao@linaro.org>,
        Suzhuangluan <suzhuangluan@hisilicon.com>
Subject: =?utf-8?B?562U5aSNOiBbUEFUQ0hdIG1tYzogZHdfbW1jLWszOiBGaXggRERSNTIgbW9k?=
 =?utf-8?Q?e_by_setting_required_clock_divisor?=
Thread-Topic: [PATCH] mmc: dw_mmc-k3: Fix DDR52 mode by setting required
 clock divisor
Thread-Index: AQHTztwoqvBFzez3EUacN3S8Mg/6rqP2h9ZA
Date:   Sun, 8 Apr 2018 08:23:53 +0000
Message-ID: <1699CE87DE933F49876AD744B5DC140FA596C5@DGGEMM506-MBS.china.huawei.com>
References: <20180329182423.21201-1-ryan@edited.us>
 <e3ec3a77-f2f3-2164-4dbb-80e1ba3ebc63@rock-chips.com>
 <CAGoBSJq+tSpvFZsJLPffTaFBg5o2Nn2eeXXvHqt4Us_dd7==1w@mail.gmail.com>
 <bed16723-6bf0-4bcf-f44c-ebcf7a1e7cc5@rock-chips.com>
 <CAGoBSJogjG9efE9EKdinTCN9Px0zsW1_=5msXjHrLZXVjLBgow@mail.gmail.com>
 <9d4bec45-42e3-da8d-ff29-1f24db27faf5@rock-chips.com>
In-Reply-To: <9d4bec45-42e3-da8d-ff29-1f24db27faf5@rock-chips.com>
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