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Miller" , Sasha Levin Subject: [PATCH AUTOSEL for 4.14 149/161] net: stmmac: discard disabled flags in interrupt status register Thread-Topic: [PATCH AUTOSEL for 4.14 149/161] net: stmmac: discard disabled flags in interrupt status register Thread-Index: AQHTz5jDrkuGghikdkCQwvrqhgXvXQ== Date: Mon, 9 Apr 2018 00:21:55 +0000 Message-ID: <20180409001936.162706-149-alexander.levin@microsoft.com> References: <20180409001936.162706-1-alexander.levin@microsoft.com> In-Reply-To: <20180409001936.162706-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0725;7:lyxTIwazGqkn4x2YxjKh91WaiH2Cn3dRpEYr6eeibSw6elFE7o7IC3E/rMcOUAzoX7AYqKoBMuxNZIWmI2oFwE28Kq/efUZUJQ/mrcFiwk/BPXsavKhyF/X2Swnaxc4hWKKvOltG5j0XuBFh8uAdfICHBk6NDopcpnSnSPC4azNXmUdW4iQBKGGB5eDhWDqItVv09R3cnu1Ocncfv+RGk3JG9VDd/7+Q3xtFfVufYLNX8Esil6mGPwXfzkoZa7FY;20:fDPMAedF8+oyhitMIzGbsMHM3bDeWgZAFMDodsZ3Fke2F01pcEFz77HdS2VzOWDe9MAyRr5HzYji0pxiqQffLbtuOR1UjUW7/w50Nn1HGBjL9ms/FobtzP5Ru02Mo/iowJs0H7ZpvtAf4Bk0Blo91xXRLh9dPFnJSc3TMHDkBMM= x-ms-office365-filtering-ht: Tenant X-MS-Office365-Filtering-Correlation-Id: b102e3bb-5764-4c0b-8da8-08d59db083c2 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7193020);SRVR:DM5PR2101MB0725; x-ms-traffictypediagnostic: DM5PR2101MB0725: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alexander.Levin@microsoft.com; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(28532068793085)(89211679590171); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(61425038)(6040522)(2401047)(5005006)(8121501046)(10201501046)(3231221)(944501327)(52105095)(93006095)(93001095)(3002001)(6055026)(61426038)(61427038)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123562045)(20161123558120)(20161123560045)(6072148)(201708071742011);SRVR:DM5PR2101MB0725;BCL:0;PCL:0;RULEID:;SRVR:DM5PR2101MB0725; x-forefront-prvs: 0637FCE711 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(39380400002)(346002)(366004)(376002)(396003)(39860400002)(199004)(189003)(6486002)(81166006)(26005)(6512007)(4326008)(6666003)(6436002)(81156014)(8676002)(97736004)(186003)(36756003)(72206003)(53936002)(107886003)(2906002)(86362001)(76176011)(110136005)(305945005)(10090500001)(486006)(3660700001)(102836004)(5660300001)(14454004)(476003)(86612001)(446003)(99286004)(68736007)(66066001)(11346002)(54906003)(2616005)(1076002)(7736002)(5250100002)(25786009)(8936002)(478600001)(2900100001)(2501003)(3280700002)(105586002)(59450400001)(316002)(106356001)(22452003)(6506007)(3846002)(10290500003)(6116002)(22906009)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:DM5PR2101MB0725;H:DM5PR2101MB1032.namprd21.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Gph49BkIM+e3D8eWteVDI1zIVFf6iOvWiQmWmK4LaM5bImVnFw7zeoo9PrLueEd6Z3weASMrIpXedMHu+5jT+cOzAg6OH6n+OXef0cgfYUhKr6AxVq5syQcZMDPyLHuHTloAPgc4OyMnP0ZgRohrUhxvoux1/spMuz84mgCgQw9DdX06G7WL+w5LfXuNT62ZEY/eoHIdZFXWk6+btOK27WZdU87aQxQBkvPdSnkD/5P0mPk5AKVMhXrTsUXWVqhWcaXlXCe4FTieO0t1YN1wRUHtYoaZ/SQYi1YRcd0aalNJK0YW+dSl/OlOG88c9ZXWVeXSFZ+Uzwf7cPpGn0SUjM4sQoChGNZr4fr1+KStt7votQx+Kz+OtC9HK1QFdvCvBomWMi44kK6irIMchGH34Gz2OyaC8FPXxhR1Qs0xZTk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: b102e3bb-5764-4c0b-8da8-08d59db083c2 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:21:55.0342 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0725 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Niklas Cassel [ Upstream commit 1b84ca187510f60f00f4e15255043ce19bb30410 ] The interrupt status register in both dwmac1000 and dwmac4 ignores interrupt enable (for dwmac4) / interrupt mask (for dwmac1000). Therefore, if we want to check only the bits that can actually trigger an irq, we have to filter the interrupt status register manually. Commit 0a764db10337 ("stmmac: Discard masked flags in interrupt status register") fixed this for dwmac1000. Fix the same issue for dwmac4. Just like commit 0a764db10337 ("stmmac: Discard masked flags in interrupt status register"), this makes sure that we do not get spurious link up/link down prints. Signed-off-by: Niklas Cassel Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac4_core.c index 2f7d7ec59962..e1d03489ae63 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -562,10 +562,12 @@ static int dwmac4_irq_status(struct mac_device_info *= hw, struct stmmac_extra_stats *x) { void __iomem *ioaddr =3D hw->pcsr; - u32 intr_status; + u32 intr_status =3D readl(ioaddr + GMAC_INT_STATUS); + u32 intr_enable =3D readl(ioaddr + GMAC_INT_EN); int ret =3D 0; =20 - intr_status =3D readl(ioaddr + GMAC_INT_STATUS); + /* Discard disabled bits */ + intr_status &=3D intr_enable; =20 /* Not used events (e.g. MMC interrupts) are not handled. */ if ((intr_status & mmc_tx_irq)) --=20 2.15.1