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From:   Sasha Levin <Alexander.Levin@microsoft.com>
To:     "stable@vger.kernel.org" <stable@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     Niklas Cassel <niklas.cassel@axis.com>,
        "David S . Miller" <davem@davemloft.net>,
        Sasha Levin <Alexander.Levin@microsoft.com>
Subject: [PATCH AUTOSEL for 4.15 177/189] net: stmmac: discard disabled flags
 in interrupt status register
Thread-Topic: [PATCH AUTOSEL for 4.15 177/189] net: stmmac: discard disabled
 flags in interrupt status register
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Date:   Mon, 9 Apr 2018 00:19:08 +0000
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From: Niklas Cassel <niklas.cassel@axis.com>

[ Upstream commit 1b84ca187510f60f00f4e15255043ce19bb30410 ]

The interrupt status register in both dwmac1000 and dwmac4 ignores
interrupt enable (for dwmac4) / interrupt mask (for dwmac1000).
Therefore, if we want to check only the bits that can actually trigger
an irq, we have to filter the interrupt status register manually.

Commit 0a764db10337 ("stmmac: Discard masked flags in interrupt status
register") fixed this for dwmac1000. Fix the same issue for dwmac4.

Just like commit 0a764db10337 ("stmmac: Discard masked flags in
interrupt status register"), this makes sure that we do not get
spurious link up/link down prints.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne=
t/ethernet/stmicro/stmmac/dwmac4_core.c
index f3ed8f7853eb..05b3e7dd9821 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -562,10 +562,12 @@ static int dwmac4_irq_status(struct mac_device_info *=
hw,
 			     struct stmmac_extra_stats *x)
 {
 	void __iomem *ioaddr =3D hw->pcsr;
-	u32 intr_status;
+	u32 intr_status =3D readl(ioaddr + GMAC_INT_STATUS);
+	u32 intr_enable =3D readl(ioaddr + GMAC_INT_EN);
 	int ret =3D 0;
=20
-	intr_status =3D readl(ioaddr + GMAC_INT_STATUS);
+	/* Discard disabled bits */
+	intr_status &=3D intr_enable;
=20
 	/* Not used events (e.g. MMC interrupts) are not handled. */
 	if ((intr_status & mmc_tx_irq))
--=20
2.15.1