Message-ID: <3F40073D.6090202@wanadoo.fr>
Date: Sun, 17 Aug 2003 22:52:45 +0000
From: Philippe Elie <phil.el@wanadoo.fr>
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To: Jamie Lokier <jamie@shareable.org>
Cc: michaelc <michaelc@turbolinux.com.cn>, linux-kernel@vger.kernel.org
Subject: Re: about PENTIUM4 cache line
References: <865464921.20010309170338@turbolinux.com.cn> <20030817202534.GC3543@mail.jlokier.co.uk>
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Jamie Lokier wrote:
> michaelc wrote:
> 
>>     I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6?   Any expanation about this would be appreciated!
> 
> 
> I don't recall seeing an answer to this.
> Was there one?

There is some confusion about P4 cache line size but

Intel Software Developer's Manual VOL 1

Page 2.12, Par 2.6:
"128-byte cache line size
  - Two 64-byte sectors"

regards,
Philippe Elie

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