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[209.132.180.67]) by mx.google.com with ESMTP id f3si318208pgu.783.2018.04.09.07.46.49; Mon, 09 Apr 2018 07:47:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752303AbeDIOmT (ORCPT + 99 others); Mon, 9 Apr 2018 10:42:19 -0400 Received: from sabertooth01.qualcomm.com ([65.197.215.72]:50647 "EHLO sabertooth01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751456AbeDIOmS (ORCPT ); Mon, 9 Apr 2018 10:42:18 -0400 X-IronPort-AV: E=Sophos;i="5.48,427,1517904000"; d="scan'208";a="125698233" Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by sabertooth01.qualcomm.com with ESMTP; 09 Apr 2018 07:42:17 -0700 Received: from westreach.qualcomm.com ([10.228.196.125]) by ironmsg01-sd.qualcomm.com with ESMTP; 09 Apr 2018 07:42:15 -0700 Received: by westreach.qualcomm.com (Postfix, from userid 467151) id 292491ED9; Mon, 9 Apr 2018 10:42:15 -0400 (EDT) From: Oza Pawandeep To: Bjorn Helgaas , Philippe Ombredanne , Thomas Gleixner , Greg Kroah-Hartman , Kate Stewart , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Dongdong Liu , Keith Busch , Wei Zhang , Sinan Kaya , Timur Tabi Cc: Oza Pawandeep Subject: [PATCH v13 4/6] PCI/DPC: Unify and plumb error handling into DPC Date: Mon, 9 Apr 2018 10:41:52 -0400 Message-Id: <1523284914-2037-5-git-send-email-poza@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523284914-2037-1-git-send-email-poza@codeaurora.org> References: <1523284914-2037-1-git-send-email-poza@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Current DPC driver does not do recovery, e.g. calling end-point's driver's callbacks, which sanitize the sw. DPC driver implements link_reset callback, and calls pci_do_recovery(). Signed-off-by: Oza Pawandeep diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 98aeec4..d02e029 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -19,6 +19,7 @@ #include #include #include "portdrv.h" +#include "./../pci.h" struct aer_broadcast_data { enum pci_channel_state state; @@ -179,11 +180,12 @@ static pci_ers_result_t default_reset_link(struct pci_dev *dev) return PCI_ERS_RESULT_RECOVERED; } -static pci_ers_result_t reset_link(struct pci_dev *dev) +static pci_ers_result_t reset_link(struct pci_dev *dev, int severity) { struct pci_dev *udev; pci_ers_result_t status; struct pcie_port_service_driver *driver = NULL; + u32 service; if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { /* Reset this port for all subordinates */ @@ -193,8 +195,12 @@ static pci_ers_result_t reset_link(struct pci_dev *dev) udev = dev->bus->self; } - /* Use the aer driver of the component firstly */ - driver = pcie_port_find_service(udev, PCIE_PORT_SERVICE_AER); + if (severity == DPC_FATAL) + service = PCIE_PORT_SERVICE_DPC; + else + service = PCIE_PORT_SERVICE_AER; + + driver = pcie_port_find_service(udev, service); if (driver && driver->reset_link) { status = driver->reset_link(udev); @@ -281,7 +287,8 @@ void pcie_do_recovery(struct pci_dev *dev, int severity) pci_ers_result_t status, result = PCI_ERS_RESULT_RECOVERED; enum pci_channel_state state; - if (severity == AER_FATAL) + if ((severity == AER_FATAL) || + (severity == DPC_FATAL)) state = pci_channel_io_frozen; else state = pci_channel_io_normal; @@ -291,8 +298,9 @@ void pcie_do_recovery(struct pci_dev *dev, int severity) "error_detected", report_error_detected); - if (severity == AER_FATAL) { - result = reset_link(dev); + if ((severity == AER_FATAL) || + (severity == DPC_FATAL)) { + result = reset_link(dev, severity); if (result != PCI_ERS_RESULT_RECOVERED) goto failed; } diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 38e40c6..517c8b4 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -13,6 +13,7 @@ #include #include "../pci.h" #include "aer/aerdrv.h" +#include "portdrv.h" struct dpc_dev { struct pcie_device *dev; @@ -45,6 +46,33 @@ static const char * const rp_pio_error_string[] = { "Memory Request Completion Timeout", /* Bit Position 18 */ }; +static int find_dpc_dev_iter(struct device *device, void *data) +{ + struct pcie_port_service_driver *service_driver; + struct device **dev; + + dev = (struct device **) data; + + if (device->bus == &pcie_port_bus_type && device->driver) { + service_driver = to_service_driver(device->driver); + if (service_driver->service == PCIE_PORT_SERVICE_DPC) { + *dev = device; + return 1; + } + } + + return 0; +} + +static struct device *pci_find_dpc_dev(struct pci_dev *pdev) +{ + struct device *dev = NULL; + + device_for_each_child(&pdev->dev, &dev, find_dpc_dev_iter); + + return dev; +} + static int dpc_wait_rp_inactive(struct dpc_dev *dpc) { unsigned long timeout = jiffies + HZ; @@ -82,12 +110,25 @@ static void dpc_wait_link_inactive(struct dpc_dev *dpc) dev_warn(dev, "Link state not disabled for DPC event\n"); } -static void dpc_work(struct work_struct *work) +/** + * dpc_reset_link - reset link DPC routine + * @pdev: pointer to Root Port's pci_dev data structure + * + * Invoked by Port Bus driver when performing link reset at Root Port. + */ +static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) { - struct dpc_dev *dpc = container_of(work, struct dpc_dev, work); - struct pci_dev *dev, *temp, *pdev = dpc->dev->port; struct pci_bus *parent = pdev->subordinate; - u16 cap = dpc->cap_pos, ctl; + struct pci_dev *dev, *temp; + struct dpc_dev *dpc; + struct pcie_device *pciedev; + struct device *devdpc; + u16 cap, ctl; + + devdpc = pci_find_dpc_dev(pdev); + pciedev = to_pcie_device(devdpc); + dpc = get_service_data(pciedev); + cap = dpc->cap_pos; pci_lock_rescan_remove(); list_for_each_entry_safe_reverse(dev, temp, &parent->devices, @@ -104,21 +145,31 @@ static void dpc_work(struct work_struct *work) dpc_wait_link_inactive(dpc); if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc)) - return; + return PCI_ERS_RESULT_DISCONNECT; if (dpc->rp_extensions && dpc->rp_pio_status) { pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, dpc->rp_pio_status); dpc->rp_pio_status = 0; } - pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, + pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT); pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, ctl | PCI_EXP_DPC_CTL_INT_EN); + + return PCI_ERS_RESULT_RECOVERED; } +static void dpc_work(struct work_struct *work) +{ + struct dpc_dev *dpc = container_of(work, struct dpc_dev, work); + struct pci_dev *pdev = dpc->dev->port; + + /* From DPC point of view error is always FATAL. */ + pcie_do_recovery(pdev, DPC_FATAL); +} static void dpc_process_rp_pio_error(struct dpc_dev *dpc) { struct device *dev = &dpc->dev->device; @@ -297,6 +348,7 @@ static struct pcie_port_service_driver dpcdriver = { .service = PCIE_PORT_SERVICE_DPC, .probe = dpc_probe, .remove = dpc_remove, + .reset_link = dpc_reset_link, }; static int __init dpc_service_init(void) diff --git a/include/linux/aer.h b/include/linux/aer.h index 8f87bbe..9cfd0b8 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -15,6 +15,8 @@ #define AER_FATAL 1 #define AER_CORRECTABLE 2 +#define DPC_FATAL 4 + struct pci_dev; struct aer_header_log_regs { -- 2.7.4