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[209.132.180.67]) by mx.google.com with ESMTP id y11-v6si1042489plk.197.2018.04.09.14.06.50; Mon, 09 Apr 2018 14:07:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=QqOhLfx9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754129AbeDIVDn (ORCPT + 99 others); Mon, 9 Apr 2018 17:03:43 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:40533 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751988AbeDIVDj (ORCPT ); Mon, 9 Apr 2018 17:03:39 -0400 Received: by mail-pl0-f67.google.com with SMTP id x4-v6so5946400pln.7 for ; Mon, 09 Apr 2018 14:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=94+r19UbYTv4XJAtubCVFGrbWGtg6tK/HTxAdkK1Zls=; b=QqOhLfx9SkrlkYx4Y7rYVgA+Qsrg9d3jROUUEztRcangtIltYocDE6hjB35gsJlZGV deFmbBTbkTmwlP3XKEwYw/UUI8MwC37o78C7a3vxn5d3XBzDqYNcClOEnaTdOnpdLEpK ivWV/rxIh8pOHDIrANMuzZaD28CSF2JUXFeQWW6k9FcYZmi/Ayr3J2lo+ih5m9nWSh1T 4xwahAPO1cJj3bk1SJxEBd6octugbyQXPrjxSD5+8z7GSCXeol4mjQzISDiPkDkeHQvI +iLsH8xbD9rsbPCAtB4N13hTBH75Wg1Oqzp+OizaI4mrR6dzb4pGYuaHKSbUvPFQxXpd QkiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=94+r19UbYTv4XJAtubCVFGrbWGtg6tK/HTxAdkK1Zls=; b=lqzODNWxQpwLMCty3Gs4tDYoo8YwDEtZqyGe95HQ6+OxwaoA23tt9HDnYviTdgn45F ufixHOZsyrsCx9Zqgj/Pg6pkzJfZaoD/0WXlnqHzzRbzuQC0vQ99gAgR5zDe+yAZCnLh aBaGoHZhLrxU14R9K8Sk1q7mn6XWHszAe07M2XhBqrM6+1IHN897WHSQ0/wZnct+EHzh d8G6s0pol7sNcdBIpFgwf/yv5DkDYN6vO1JaNH3iVdoVceTGdnKqnHDXkFW47klS55h4 prP7dymdjyn/Ce9f9Reh9Z4NakNMuky9ciii9DYXo2XsN91NtiBaSo6O0/N0QLAnf9L2 JxsQ== X-Gm-Message-State: AElRT7EcWEqZy7KMe/hidzrnUwkLywWhQt3CEPcF4B38UPb5LjnGUNbs 5nXT8xGs0fxVxQ1UfLDoFHBbFA== X-Received: by 2002:a17:902:227:: with SMTP id 36-v6mr39132887plc.134.1523307819115; Mon, 09 Apr 2018 14:03:39 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c64sm1979939pfe.152.2018.04.09.14.03.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Apr 2018 14:03:38 -0700 (PDT) Date: Mon, 09 Apr 2018 14:03:38 -0700 (PDT) X-Google-Original-Date: Mon, 09 Apr 2018 14:03:34 PDT (-0700) Subject: Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support In-Reply-To: <20180409070710.GA3844@andestech.com> CC: albert@sifive.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, jolsa@redhat.com, namhyung@kernel.org, sols@sifive.com, corbet@lwn.net, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, nickhu@andestech.com, greentime@andestech.com From: Palmer Dabbelt To: alankao@andestech.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 09 Apr 2018 00:07:11 PDT (-0700), alankao@andestech.com wrote: > On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote: >> On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alankao@andestech.com wrote: >> >This patch provide a basic PMU, riscv_base_pmu, which supports two >> >general hardware event, instructions and cycles. Furthermore, this >> >PMU serves as a reference implementation to ease the portings in >> >the future. >> > >> >riscv_base_pmu should be able to run on any RISC-V machine that >> >conforms to the Priv-Spec. Note that the latest qemu model hasn't >> >fully support a proper behavior of Priv-Spec 1.10 yet, but work >> >around should be easy with very small fixes. Please check >> >https://github.com/riscv/riscv-qemu/pull/115 for future updates. >> > >> >Cc: Nick Hu >> >Cc: Greentime Hu >> >Signed-off-by: Alan Kao >> >> We should really be able to detect PMU types at runtime (via a device tree >> entry) rather than requiring that a single PMU is built in to the kernel. >> This will require a handful of modifications to how this patch works, which >> I'll try to list below. > >> >+menu "PMU type" >> >+ depends on PERF_EVENTS >> >+ >> >+config RISCV_BASE_PMU >> >+ bool "Base Performance Monitoring Unit" >> >+ def_bool y >> >+ help >> >+ A base PMU that serves as a reference implementation and has limited >> >+ feature of perf. >> >+ >> >+endmenu >> >+ >> >> Rather than a menu where a single PMU can be selected, there should be >> options to enable or disable support for each PMU type -- this is just like >> how all our other drivers work. >> > > I see. Sure. The descriptions and implementation will be refined in v3. > >> >+struct pmu * __weak __init riscv_init_platform_pmu(void) >> >+{ >> >+ riscv_pmu = &riscv_base_pmu; >> >+ return riscv_pmu->pmu; >> >+} >> >> Rather than relying on a weak symbol that gets overridden by other PMU >> types, this should look through the device tree for a compatible PMU (in the >> case of just the base PMU it could be any RISC-V hart) and install a PMU >> handler for it. There'd probably be some sort of priority scheme here, like >> there are for other driver subsystems, where we'd pick the best PMU driver >> that's compatible with the PMUs on every hart. >> >> >+ >> >+int __init init_hw_perf_events(void) >> >+{ >> >+ struct pmu *pmu = riscv_init_platform_pmu(); >> >+ >> >+ perf_irq = NULL; >> >+ perf_pmu_register(pmu, "cpu", PERF_TYPE_RAW); >> >+ return 0; >> >+} >> >+arch_initcall(init_hw_perf_events); >> >> Since we only have a single PMU type right now this isn't critical to handle >> right away, but we will have to refactor this before adding another PMU. > > I see. My rough plan is to do the device tree parsing here, and if no specific > PMU string is found then just register the base PMU proposed in this patch. > How about this idea? Sounds good. We know the generic PMU will work on all RISC-V harts, so there's no need to add an explicit device tree entry for it. Then we can figure out how to add device tree entries for custom performance monitors later :)